DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 304

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 17 Development Support
Figure 17-2
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD
pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.
304
SYNCHRONIZATION
PERCEIVED START
(TARGET MCU)
BDC CLOCK
UNCERTAINTY
TRANSMIT 1
TRANSMIT 0
OF BIT TIME
HOST
HOST
shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 17-2. BDC Host-to-Target Serial Bit Timing
TARGET SENSES BIT LEVEL
10 CYCLES
EARLIEST START
OF NEXT BIT
Freescale Semiconductor