DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 263

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

14.6.1
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of
byte transfer.
14.6.2
When the calling address matches the programmed slave address (IIC address register), the IAAS bit in
the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW
bit and set its Tx mode accordingly.
14.6.3
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
This bit must be cleared by software by writing a one to it.
Freescale Semiconductor
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SDA sampled as a low when the master drives a high during an address or data transmit cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
A START cycle is attempted when the bus is busy.
A repeated START cycle is requested in slave mode.
A STOP condition is detected when the master did not request it.
Byte Transfer Interrupt
Address Detect Interrupt
Arbitration Lost Interrupt
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Chapter 14 Inter-Integrated Circuit (S08IICV1)
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