72T18105L5BBGI Integrated Device Technology (Idt), 72T18105L5BBGI Datasheet - Page 20

• Manufacturer Part Number: 72T18105L5BBGI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 128K x 18/256K x 9 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T18105L5BBGI

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Mb
• Organization: 128Kx18|256Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. When programming the IDT72T1895 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72T1895 with an output
2. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
D/Q17
D/Q17
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895
bus width of x9 and input bus width of x18, 4 read cycles will be required. A total of 6 program/read cycles will be required if both the input and output bus widths are set to x9.
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
1st Parallel Offset Write/Read Cycle
D/Q16
D/Q16
16
16
16
15
15
16
# of Bits Used:
12 bits for the IDT72T1845
13 bits for the IDT72T1855
14 bits for the IDT72T1865
15 bits for the IDT72T1875
16 bits for the IDT72T1885
17 bits for the IDT72T1895
18 bits for the IDT72T18105
19 bits for the IDT72T18115
20 bits for the IDT72T18125
Note: All unused bits of the
LSB & MSB are don’t care
16
16
15
14
14
8
8
15
14
14
13
13
x9 to x9 Mode
15
15
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
13
13
12
7
12
7
FULL OFFSET REGISTER
FULL OFFSET REGISTER
Data Inputs/Outputs
Data Inputs/Outputs
FULL OFFSET REGISTER
12
11
12
11
14
14
10
10
11
11
6
6
⎯
(1)
10
⎯
10
9
9
x18 Bus Width
D/Q8
D/Q8
13
13
x9 Bus Width
5
5
9
9
8
8
8
8
12
12
4
4
7
7
7
7
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
11 bits for the IDT72T1845
12 bits for the IDT72T1855
13 bits for the IDT72T1865
14 bits for the IDT72T1875
15 bits for the IDT72T1885
16 bits for the IDT72T1895
17 bits for the IDT72T18105
18 bits for the IDT72T18115
19 bits for the IDT72T18125
# of Bits Used:
Note: All unused bits of the
LSB & MSB are don’t care
6
6
6
6
# of Bits Used
11
11
All Other Modes
3
3
5
5
5
5
4
4
4
4
10
10
2
2
3
3
3
3
2
2
2
2
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
1
9
1
9
1
1
1
1
Non-Interspersed
Parity
Interspersed
Parity
20
D/Q17
D/Q17
D/Q17
D/Q17
IDT72T1895/72T18105/72T18115/72T18125
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
5th Parallel Offset Write/Read Cycle
6th Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
IDT
D/Q16
D/Q16
D/Q16
16
D/Q16
16
72T18105/72T18115/72T18125
15
16
15
16
16
16
8
8
15
14
15
14
2Kx18/4Kx9, 4Kx18/
14
13
14
13
EMPTY OFFSET (LSB) REGISTER
EMPTY OFFSET (MSB) REGISTER
FULL OFFSET (LSB) REGISTER
FULL OFFSET (MSB) REGISTER
15
EMPTY OFFSET REGISTER
15
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
7
7
13
13
12
12
FULL OFFSET REGISTER
FULL OFFSET REGISTER
FULL OFFSET REGISTER
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
12
11
12
11
14
14
6
6
10
10
11
11
10
10
9
9
13
13
4666 drw 06
5
5
D/Q8
D/Q8
9
9
8
8
8
8
20
20
12
12
4
4
7
7
7
7
6
6
6
COMMERCIAL AND INDUSTRIAL
6
# of Bits Used
19
19
11
11
3
3
5
5
5
5
4
4
4
4
18
18
10
10
⎯
2
2
19
19
3
3
19
19
TEMPERATURE RANGES
3
3
x18 Bus Width
18
18 17
18
18 17
2
2
2
2
17
17
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
1
9
1
9
17
17
FEBRUARY 10, 2009
1
1
1
1
(1)
⎯
Non-Interspersed
Parity
Interspersed
Parity
x9 Bus Width
5909 drw07