72T18105L5BBGI Integrated Device Technology (Idt), 72T18105L5BBGI Datasheet - Page 54

• Manufacturer Part Number: 72T18105L5BBGI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 128K x 18/256K x 9 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T18105L5BBGI

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Mb
• Organization: 128Kx18|256Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 2,048 when the x18 Input or x18 Output bus Width is selected, 4,096
for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the
IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the
IDT72T18125. When both x9 Input and x9 Output bus Widths are selected,
depths greater than 4,096 can be adapted for the IDT72T1845, 8,192 for the
IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875,
65,536 for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the
IDT72T8105, 524,288 for the IDT72T18115 and 1,048,576 for the
IDT72T18125. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO. Figure 37 shows
a depth expansion using two IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FWFT/SI
DATA IN
WRITE CLOCK
WRITE ENABLE
The IDT72T1845 can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all FIFOs
For an empty expansion configuration, the amount of time it takes for OR of
INPUT READY
4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18, 524,288 x 18 and 1,048,576 x 18
n
8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9, 262,144 x 9, 524,288 x 9, 1,048,576 x 9 and 2,097,152 x 9
IR
Dn
WEN
WCLK
72T18105
72T18115
72T18125
FWFT/SI
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
IDT
TRANSFER CLOCK
Figure 37. Block Diagram of Depth Expansion
RCLK
For both x9 Input and x9 Output bus Widths:
REN
RCS
For the x18 Input or x18 Output bus Width:
OE
OR
Qn
GND
n
54
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
Note that extra cycles should be added for the possibility that the t
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The "ripple down" delay is only noticeable for the first word written to an empty
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
2Kx18/4Kx9, 4Kx18/
WCLK
IR
WEN
Dn
(N – 1)*(4*transfer clock) + 3*T
(N – 1)*(3*transfer clock) + 2 T
72T18105
72T18115
72T18125
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
FWFT/SI
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
RCS
OR
OE
Qn
TEMPERATURE RANGES
FEBRUARY 10, 2009
RCLK
READ CHIP SELECT
OUTPUT ENABLE
n
WCLK
RCLK
OUTPUT READY
WCLK
is the RCLK period.
READ ENABLE
READ CLOCK
DATA OUT
5909 drw41
is the WCLK
SKEW1
SKEW1