72T18105L5BBGI Integrated Device Technology (Idt), 72T18105L5BBGI Datasheet - Page 5

• Manufacturer Part Number: 72T18105L5BBGI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 128K x 18/256K x 9 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T18105L5BBGI

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Mb
• Organization: 128Kx18|256Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

shown in Table 1.
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin.
to select the parity bit in the word loaded into the parallel port (D
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D
programming of the flag offsets. If Non-Interspersed Parity mode is selected,
then D
is selected during Master Reset by the state of the IP input pin. This mode is
relevant only when the input width is set to x18 mode.
automatically power down. Once in the power down state, the standby supply
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
The device can be configured with different input and output bus widths as
A Big-Endian/Little-Endian data word format is provided. This function is
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
If, at any time, the FIFO is not actively performing an operation, the chip will
8
is assumed to be a valid bit and D
16
and D
17
are ignored. IP mode
8
during the parallel
0
-Dn) when
5
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
72T18105/72T18115/72T18125 are fabricated using IDT’s high speed sub-
micron CMOS technology.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
A JTAG test port is provided, here the FIFO has fully functional Boundary
The TeraSync FIFO has the capability of operating its ports (write and/or
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009