MC100ES6254FA IDT, Integrated Device Technology Inc, MC100ES6254FA Datasheet - Page 3
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MC100ES6254FA
Manufacturer Part Number
MC100ES6254FA
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet
1.MC100ES6254FA.pdf
(9 pages)
Specifications of MC100ES6254FA
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
3000MHz
Output Logic Level
LVPECL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
LQFP
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Signal Type
LVPECL
Mounting
Surface Mount
Pin Count
32
Quiescent Current
85mA
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC100ES6254FA
Manufacturer:
PREWELL
Quantity:
5 000
Company:
Part Number:
MC100ES6254FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
IDT™ 2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6254
2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
a.
Table 1. PIN CONFIGURATION
CLK0,
CLK1,
OEA, OEB
SEL0, SEL1
QA[0-2],
QB[0-2],
GND
V
Table 2. FUNCTION TABLE
OEA
OEB
SEL0, SEL1
Table 3. CLOCK SELECT CONTROL
Table 4. ABSOLUTE MAXIMUM RATINGS
TIMING SOLUTIONS
Symbol
CC
V
I
V
V
OUT
SEL0
I
T
OUT
CC
IN
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
IN
S
0
0
1
1
Control
CLK0
CLK1
Pin
QA[0-2]
QB[0-2]
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
SEL1
0
1
0
1
Input
Input
Input
Input
Output
Supply
Supply
Default
I/O
00
0
0
Characteristics
LVPECL
LVPECL
LVCMOS
LVCMOS
LVPECL
GND
VCC
QA[0-2],
asynchronous to the reference clock without generation
of output runt pulses
QA[0-2],
asynchronous to the reference clock without generation
of output runt pulses
QA[0:2] and QB[0:2]
CLK0 routed to
Freescale Semiconductor, Inc.
Type
For More Information On This Product,
QA[0:2]
QB[0:2]
Qx[0-2]
Qx[0-2]
---
a
Differential reference clock signal input 0
Differential reference clock signal input 1
Output enable
Clock switch select
Differential clock outputs (banks A and B)
Negative power supply
Positive power supply. All V
DC and AC operation
are active. Deassertion of
are active. Deassertion of
0
3
QA[0:2] and QB[0:2]
CLK1 routed to
CC
OE
OE
Min
-0.3
-0.3
-0.3
-65
pins must be connected to the positive power supply for correct
QB[0:2]
QA[0:2]
can be
can be
Refer to Table 3
---
QA[0-2] = L,
of
without generation of output runt pulses
QA[0-2] = L,
of
without generation of output runt pulses
Function
OE
OE
can be asynchronous to the reference clock
can be asynchronous to the reference clock
V
V
CC
CC
Max
±20
±50
125
QA[0-2]
QA[0-2]
3.6
+0.3
+0.3
= H (outputs disabled). Assertion
= H (outputs disabled). Assertion
Dual 1:3 buffer (crossed)
Application Mode
1:6 fanout of CLK0
1:6 fanout of CLK1
1
Dual 1:3 buffer
Unit
mA
mA
°C
V
V
V
MC100ES6254/D
MC100ES6254
Condition
NETCOM
3