ISL3685IR96 Intersil, ISL3685IR96 Datasheet - Page 6

• Manufacturer Part Number: ISL3685IR96
• Manufacturer: Intersil

Specifications of ISL3685IR96

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NOTE:
Phase Lock Loop Electrical Specifications
NOTES:
PLL Synthesizer Table
Reference Oscillator Sensitivity, CMOS Inputs, Single
Ended or Complementary
Reference Oscillator Duty Cycle
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Mismatch
Charge Pump Output Compliance
Charge Pump Supply Voltage
Serial Interface Clock Width
Serial Interface Data/Clk Set-Up Time t
Serial Interface Data/Clk Hold Time t
Serial Interface Clk/LE Set-Up Time t
Serial Interface LE Pulse Width t
SERIAL BITS
R Counter
A/B Counter
Operational
Mode
4. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is
5. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of
6. CMOS Reference Oscillator input levels are given in the General Electrical Specification section.
7. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function
latched into defined registers on the rising edge of LE.
the power down state without requiring the registers to be rewritten.
of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers.
PE1
X
0
1
1
0
LSB 1
DEFINITION
REGISTER
0
0
1
PARAMETER
2
0
1
0
M(0)
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14)
A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3)
3
EW
6
CH
PE2
ES
X
0
1
0
1
4
0
CS
M(2) M(3) M(4) M(5) M(6) M(7) M(8)
5
6
POWER ENABLE TRUTH TABLE
(SERIAL BUS)
7
(See Notes 4 through 12) (Continued)
CMOS Inputs
250 A Selection 25%
500 A Selection 25%
750 A Selection 25%
1mA Selection 25%
Charge Pump V
High Level t
Low Level t
PLL_PE
TEST CONDITIONS
8
1
1
1
1
0
ISL3685
9
CWL
CWH
10
CC
Power Down State, PLL in Save Mode, Active Serial Interface
Receive State
Transmit State
PLL Inactive, Inactive RX, TX, Active Serial Interface
PLL Disabled, Disabled PLL Registers, Active Serial Interface
= V
11
CC2
12
0
0.375
13
MIN
0.18
0.56
0.75
0
0.5
2.7
40
20
20
20
10
20
20
-
-
B(4)
14
0
B(5)
15
CMOS
STATUS
0
TYP
0.25
0.50
0.75
1.0
-
-
-
-
-
-
-
-
-
-
M(13) M(14) M(15)
B(6)
16
B(7)
V
17
CC2
0.625
MAX
0.32
0.94
1.25
3.6
60
15
-
-
-
-
-
-
-
-0.5
B(8)
18
X (Don’t Care)
B(9) B(10)
19
X
UNITS
Note 7
mA
mA
mA
mA
ns
ns
ns
ns
ns
ns
%
%
V
V
MSB
X