5962-8953202QA QP SEMICONDUCTOR, 5962-8953202QA Datasheet - Page 32

• Manufacturer Part Number: 5962-8953202QA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8953202QA

• Lead Free Status / RoHS Status: Not Compliant

DSCC FORM 2234
APR 97
Mnemonic
D0 – D7
CSN
R/WN
A1 – A4
RESETN
DTACKN
INTRN
IACKN
X1/CLK
X2
RxDA
RxDB
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
Pin number
25, 16, 24, 17,
23, 18, 22, 19
1, 3, 5, 6
STANDARD
35
34
21
37
32
33
31
10
8
9
1/
Type
I/O
O
O
I
I
I
I
I
I
I
I
I
TABLE III. Pin descriptions - Continued.
Data Bus: Bidirectional three-state data bus used to transfer commands,
data and status between the DUART and the CPU. D0 is the least
significant bit.
Chip Select: Active low input signal. When low, data transfers between
the CPU and the DUART are enabled on D0 – D7 as controlled by the
R/WN and A1 – A4 inputs. When high, places the D0 – D7 lines in the
three-state condition.
Read/Write: A high input indicates a read cycle and a low input indicates
a write cycle, when a cycle is initiated by assertion of the CSN input.
Address Inputs: Selects the DUART internal registers and ports for
read/write operations.
Reset: A low clears internal registers (SRA, SRB, IMR, ISR, OPR,
OPCR), initializes the IVR to hex 0F, puts OP0 – OP7 in the high state,
stops the counter/timer, and puts channel A and B in the inactive state,
with the TxDA and TxDB outputs in the “mark” (high) state.
Data Transfer Acknowledge: Three-state active low output asserted in
write, read, or interrupt cycles to indicate proper transfer of data between
the CPU and the DUART.
Interrupt Request: Active low, open drain output which signals the CPU
that one or more of the eight maskable interrupting conditions are true.
Interrupt Acknowledge: Active low input indicating an interrupt
acknowledge cycle. In response, the DUART will place the interrupt
vector on the data bus and will assert DTACKN if it has an interrupt
pending.
Crystal 1: Crystal or external clock input. A crystal or clock of the
specified limits must be supplied at all times. If a crystal is used, a
capacitor must be connected from this pin to ground (see figure 4 herein).
Crystal 2: Connection for other side of the crystal. If a crystal is used, a
capacitor must be connected from this pin to ground (see figure 4 herein).
Channel A Receiver Serial Data Input: The least significant bit is received
first. “Mark” is high, “space” is low.
Channel B Receiver Serial Data Input: The least significant bit is received
first. “Mark” is high, “space” is low.
If an external clock is used, this pin should be grounded.
For device type 03.
SIZE
A
Name and function
REVISION LEVEL
C
SHEET
5962-89532
32