DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet
DJLXT360LE.A2 S E001
Specifications of DJLXT360LE.A2 S E001
Related parts for DJLXT360LE.A2 S E001
DJLXT360LE.A2 S E001 Summary of contents
Page 1
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applica- tions The LXT360 is a fully integrated, combination transceiver for T1/E1 ISDN Primary Rate Interface (ISDN PRI) and general T1/E1 long and short haul applications. It operates over 0.63 mm ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
Page 3
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Contents 1.0 Pin Assignments and Signal Descriptions 1.1 Mode Dependent Signals ...................................................................................... 9 2.0 Functional Description 2.1 Initialization..........................................................................................................14 2.1.1 Reset Operation .....................................................................................14 2.2 Transmitter ..........................................................................................................14 2.2.1 Transmit Digital Data ...
Page 4
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 3.0 Register Definitions 4.0 Application Information 4.1 Transmit Return Loss.......................................................................................... 36 4.2 Transformer Data ................................................................................................ 36 4.3 Application Circuits.............................................................................................. 36 4.3.1 Hardware Mode Circuit........................................................................... 38 4.3.2 Host Mode Circuit................................................................................... ...
Page 5
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Tables 1 LXT360 Clock and Data Pins by Mode1 ............................................................... 9 2 LXT360 Control Pins by Mode ..............................................................................9 3 LXT360 Signal Descriptions ................................................................................10 4 CLKE Pin Settings1.............................................................................................18 5 Control ...
Page 6
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Revision History Revision Date 6 Description Datasheet ...
Page 7
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 1. LXT360 Block Diagram INTERNAL TCLK PATTERN B8ZS/HDB3 GENERATOR TPOS UNIPOLAR (QRSS) ENCODER TNEG MODE QRSS ENCODER ENABLE ENABLE RLOOP NLOOP ENABLE ENABLE TRSTE LOOPBACK JASEL MCLK DECODER ...
Page 8
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT360 Pin Assignmentsa nd Markings RNEG / BPV RPOS / RDATA MODE RNEG / BPV RPOS / RDATA RCLK TRSTE JASEL ...
Page 9
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 1.1 Mode Dependent Signals As shown in Figure according to the selected mode(s) of operation. These pins, associated signal names and operating modes are summarized in Table 1. LXT360 ...
Page 10
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 3. LXT360 Signal Descriptions Pin # Symbol PLCC QFP 1 39 MCLK 2 41 TCLK 3 42 TPOS/TDATA/ INSLER TNEG/INSBPV MODE 6 3 RNEG/BPV ...
Page 11
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 3. LXT360 Signal Descriptions (Continued) Pin # Symbol PLCC QFP 8 5 RCLK 9 7 TRSTE 11 10 JASEL 12 13 LOS/QPD 13 15 TTIP 16 19 TRING ...
Page 12
... CS is High. Timing is shown in page 48. HARDWARE MODES: Remote Loopback. When held High, the clock and data inputs from the framer (TPOS/TNEG or TDATA) are ignored and the data received from the twisted-pair line is transmitted back onto the line at the RCLK frequency. Connect to Midrange DI detection (NLOOP). ...
Page 13
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 3. LXT360 Signal Descriptions (Continued) Pin # Symbol PLCC QFP 27 37 LLOOP/SCLK 28 38 TAOS/QRSS/ CLKE 11, 12, 14, 17, 22, 10 n/c ...
Page 14
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 2.0 Functional Description The LXT360 is a fully integrated, PCM transceiver for long- or short-haul, 1.544 Mbps (T1) or 2.048 Mbps (E1) applications allowing full-duplex transmission of digital data ...
Page 15
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 2.2.2 Transmit Monitoring The transmitter includes a short circuit limiter that limits the current sourced into a low impedance load. The limiter automatically resets when the load current drops ...
Page 16
... Alarm Indication Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled or disabled in the receive data path or the transmit path. Received data may be routed to either the B8ZS or HDB3 decoder or neither. Finally, the device may send the digital data to the framer as either unipolar or bipolar data. ...
Page 17
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 2.4 Jitter Attenuation A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides the jitter attenuation function. The JAL requires no special circuitry, such as an external quartz ...
Page 18
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Figure 4 shows the serial port data structure. The registers are accessible through a 16-bit word composed of an 8-bit Command/Address byte (bits R/ W and A1-A7) and a ...
Page 19
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 4. Serial Port Data Structure CS SCLK Address / Command Byte SDI R High Impedance SDO R Read operation R Write ...
Page 20
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 2.7 Diagnostic Mode Operation The LXT360 offers multiple diagnostic modes as listed in modes are only available in Host mode. In Hardware mode, the diagnostic modes are selected by ...
Page 21
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 2.7.1 Loopback Modes 2.7.1.1 Local Loopback (LLOOP) See Figure 5 and Figure (TCLK and TPOS/TNEG or TDATA) loop back through the jitter attenuator (if enabled) and appear at RCLK ...
Page 22
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Figure 6. Local Loopback 2.7.1.2 Analog Loopback (ALOOP) See Figure 7. Analog loopback (ALOOP) exercises the maximum number of functional blocks. ALOOP operation disconnects the RTIP/RRING inputs from the ...
Page 23
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 2.7.1.3 Remote Loopback (RLOOP) See Figure 8. When RLOOP is active, the device ignores the transmit data and clock inputs (TCLK and TPOS/TNEG or TDATA), and bypasses the in-line ...
Page 24
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Figure 9. Dual Loopback 2.7.2 Internal Pattern Generation and Detection 2.7.2.1 Transmit All Ones (TAOS) See Figure 10. When TAOS is active, the transceiver ignores the TPOS and TNEG ...
Page 25
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 A Low-to-High transition on the INSBPV pin will insert a bipolar violation in the QRSS pattern. Note that the BPV insertion occurs regardless of whether the device is in ...
Page 26
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications With this mode is active, logic errors and bipolar violations can be inserted into the transmit data stream. Inserting a logic error requires a Low-to-High transition of the INSLER ...
Page 27
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 2.7.3.5 HDB3 Code Violation Detection (CODEV) An HDB3 code violation (CODEV) occurs when two consecutive bipolar violations of the same polarity are received (refer to ITU O.161). When CODEV ...
Page 28
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 2.7.4.2 Alarm Indication Signal Detection (AIS) This function is only available in Host mode. The receiver detects an AIS pattern when it receives fewer than three 0s in any ...
Page 29
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 The most reliable test will result when a separate TCLK and MCLK are applied and the Line Build-Out (LBO) is set to -22.5 dB (CR1.EC4:1 = 011x). Datasheet 29 ...
Page 30
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 3.0 Register Definitions The LXT360 contains five read/write and three read-only registers that are accessible in Host mode via the serial I/O port. address byte are valid (the address ...
Page 31
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 9. Control Register #1 Read/Write, Address (A7-A0) = x010000x Bit Name 0 EC1 1 EC2 Sets mode (T1 or E1) and equalizer (see 2 EC3 3 EC4 1 ...
Page 32
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 11. Control Register #2 Read/Write, Address (A7-A0) = x010001x Bit Name 1 = Enable Remote loopback mode 1 0 ERLOOP 0 = Disable Remote loopback mode 1 = ...
Page 33
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 13. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x Bit Name 1 = Clear/Mask Loss of Signal interrupt. 0 CLOS 0 = Enable Loss of Signal interrupt. 1 ...
Page 34
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 15. Performance Status Register Read Only, Address (A7-A0) = x010101x Bit Name 1 = Loss of Signal occurred. 0 LOS 0 = Loss of Signal did not occur. ...
Page 35
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 17. Control Register #4 Read/Write, Address (A7-A0) = x010111x Bit Name 4 - Reserved. Set to 0 for normal operation, ignore when reading Reserved. Set to ...
Page 36
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 4.0 Application Information 4.1 Transmit Return Loss Table 18 shows the specification for transmit return loss in E1 applications. The G.703/CH PTT specification is a Swiss Telecommunications Ministry specification. ...
Page 37
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 20. Transmit Return Loss (2.048 Mbit/s–Long-Haul) High Return Loss Configuration EC4:1 Xfrmr/Rt 1:2/ 15 1001 1:1.53/15 Table 21. Transmit Return Loss (2.048 Mbit/s–Long-Haul) EC4:1 Xfrmr/Rt 1:2/ 1010 9.1 ...
Page 38
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 24. Recommended Transformers for LXT360 Tx/Rx Turns Ratio 1:1.53 1:1.15 Tx 1:2 1:2.3 Rx 1:1 4.3.1 Hardware Mode Circuit Figure 12 shows a typical LXT360 Hardware mode application ...
Page 39
... Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 12. Typical T1/E1 Hardware Mode Application 2.048MHz/ 1.544 MHz TCLK TPOS TNEG T1/E1 Framer RCLK RPOS RNEG 68 F 0.1 F NOTES: 1. See Table 19 through Table =100 for T 120 for E-1 / 120 for E coax 3 ...
Page 40
... Note that if the application includes surge protection, such as a varistor or sidactor on the TTIP/ TRING lines, it may be necessary to reduce the value of the capacitor C completely. Excessive capacitance at C Figure 13. Typical T1/E1 Host Mode Application 2.048 MHz/ 1.544 MHz TCLK TPOS TNEG +5 V T1/E1 Framer RCLK RPOS RNEG 68 F 0.1 F NOTES: 1. See Table 19 through Table 24 2 ...
Page 41
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 5.0 Test Specifications Note: Table 25 through Table 35 specifications of the LXT360 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed ...
Page 42
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 26. Recommended Operating Conditions (Continued) Parameter Short Haul 3 T1 low power Long Haul Total power Short Haul 4 T1 dissipation standard power Long Haul Short Haul/ 5 ...
Page 43
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 28. Analog Characteristics Parameter Recommended output load on TTIP/TRING DSX-1, DS1 AMI output pulse amplitudes CEPT (ITU kHz 8 kHz - 40 kHz 2 ...
Page 44
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Figure 14. 2.048 MHz E1 Pulse (See Table 29 100% 50% 0% Table 29. 2.048 MHz E1 Pulse Mask Specifications Parameter Test load impedance Nominal peak mark ...
Page 45
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 15. 1.544 MHz T1 Pulse (DS1 and DSX-1) (See Table 30) 1.5 Normalized Amplitude 1.0 0.5 0.5 -0.5 0.0 Time (in Unit Intervals) -0.5 Table 30. 1.544 MHz ...
Page 46
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 31. T1 Operation Master and Transmit Clock Timing Characteristics (See Figure 16) Parameter Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG ...
Page 47
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Table 33. Receive Timing Characteristics for T1 Operation (See Figure 17) Parameter 2, 3 Receive clock duty cycle 2, 3 Receive clock pulse width Receive clock pulse width high ...
Page 48
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Table 35. Serial I/O Timing Characteristics (See Figure 18 and Figure 19) Parameter Rise/fall time—any digital output SDI to SCLK setup time SCLK to SDI hold time SCLK low ...
Page 49
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 20. Typical T1 Jitter Tolerance 1000 UI 500 UI Jitter @ 10 Hz 138 UI 100 0.4 UI ...
Page 50
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Figure 21. Typical E1 Jitter Tolerance Datasheet ...
Page 51
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 22. Typical E1 Jitter Attenuation Figure 23. T1 Jitter Attenuation Datasheet 51 ...
Page 52
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications 6.0 Mechanical Specifications Figure 24. Plastic Leaded Chip Carrier (PLCC) Package Specifications 28-Pin PLCC • Part Number LXT360PE • Extended Temperature Range (-40 ° ° ...
Page 53
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360 Figure 25. Plastic Quad Flat Package (PQFP) Specifications 44-Pin PQFP • Part Number LXT360QE • Extended Temperature Range (-40 ° ° ...
Page 54
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications Figure 26. Low-Profile Quad Flat Package (LQFP) Specifications 44-Pin LQFP • • D/2 E1 Dimension ...