JL82572EI Intel, JL82572EI Datasheet - Page 50

• Manufacturer Part Number: JL82572EI
• Manufacturer: Intel

Specifications of JL82572EI

• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Compliant

15.
Clarification: D3->D0 transition will cause a PHY reset even in Keep PHY Link Up mode. When Critical
16.
Clarification: The 82571/82572 receiver detection circuit was designed according to the PCIe
82571/82572 Specification Update
Datasheet
52
Critical Session (Keep PHY Link Up) Mode Does Not Block All
PHY Resets Caused by PCIe Resets
Receiver Detection Circuit Design and Established Link Width.
latency for completions in the system in which the 82571EB/82572EI is installed. This will
ensure that the 82571EB/82572EI receives the completions for the requests it sends out,
avoiding a completion timeout scenario. If the latency for completions is above 21 ms,
this can result in the device timing out prior to a completion returning. In the event of a
completion timeout, per direction in the PCIe specification, the device assumes the
original completion is lost, and resends the original request. In this condition, if the
completion for the original request arrives at the 82571EB/82572EI devices, this will
result in two completions arriving for the same request, which may cause unpredictable
system behavior.
lower than 21 ms, the PCIe completion timeout mechanism should be disabled by setting
the GCR.Disable_timeout_mechanism.
Intel
Source Software Developer's Manual.
Session Mode (Keep PHY Link Up) is enabled (via the SMBUS Management Control
command), PCIe resets should not cause a PHY reset. However, the following event will
still cause a PHY reset:
11 to 00 by a configuration write.
during a reboot cycle, so it is expected that no effect will be seen in most circumstances.
Specification Rev. 1.1, which requires that an un-terminated receiver have an input
impedance of at least 200 Kohm. PCIe Specification Rev. 2.0 allows the input impedance
to be as low as 1 Kohm at input voltages in the range -150 - 0 mV and does not specify a
minimum input impedance below -150 mV. As a result, a powered-down receiver lane
with low input impedance at negative voltages could be compliant to Rev 2.0 and yet be
falsely detected by the 82571/82572 as a terminated lane.
within 5 ms after fundamental reset according to the PCIe Specification. However, there
are some chipset devices that require significantly more time to prepare the termination
and expect the link partner to remain in the LTSSM Detect state as long as none of the
lanes are terminated. When used with such devices, the 82571/82572 might falsely
detect a receiver on one or more lanes and leave the Detect state. This can lead to
establishing a link that is less than full width.
In this case, it is recommended that a Hot Reset be performed after a link has been
established in order to force the 82571/82572 to detect the receivers again when they
are properly terminated. As a result, a full-width link can be established.
Loss of link can cause a loss of the MNG session. These events do not normally occur
This is normally not an issue since any connnected lanes should be properly terminated
Transition from D3 to D0 without a general PCIe reset, i.e. PMCSR[1:0] is changed from
The completion timeout value in a system must be above the expected maximum
Therefore, if the PCIe completion latency for a system cannot be guaranteed to be
For more details on Completion Timeout operation in the 82571EB/82572EI refer to the
®
82571EB/82572EI Controller Datasheet and the PCIe* GbE Controllers Open
82571/82572 Specification Update
Revision: 6.3US
July 2010
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