RCLXT16726FE Intel, RCLXT16726FE Datasheet - Page 2

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RCLXT16726FE

Manufacturer Part Number
RCLXT16726FE
Description
Manufacturer
Intel
Datasheet

Specifications of RCLXT16726FE

Operating Supply Voltage (typ)
1.8/3.3V
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
RCLXT16726FE
Manufacturer:
INTEL/英特尔
Quantity:
20 000
Product Overview (Cont’d)
together with an external VCXO can be used to clean the
reference clock coming from the framer. In order to support
multiple line speeds without using external selection
components, the transmitter has been equipped with three
VCXO clock inputs.
In order to facilitate board design, the Intel LXT16726/727
chipset has been equipped with bit swap and bit inversion.
These features flip the polarity and/or position of the individual
data I/Os to ensure flexible PCB routing.
Features
Combined power dissipation of 1.8W
Integrated LIA with high input sensitivity
Single or dual power supply
High output swing
Multi-rate 9.95 - 11.1Gbps
132-pin 13x13mm (LXT16726, LXT16727, LXT16727A) or
142-pin 10x10mm (LXT16726, LXT16727) PBGA package
Three VCXO clock inputs
OIF SFI-4 compliant interface
9-bit FIFO and DPA
Product Brief
Intel
®
LXT16726/727 Serializer/Deserializer Chipset
The devices allow operation at any line rate between 9.95
and 11.1Gbps. This provides for a flexible module with
reduced design and production costs.
Benefits
Ideal for MSA Module applications where performance and
power are key
Helps eliminate the need for an external LIA therefore
reducing cost
Helps increase design flexibility and ensures lowest possible
power dissipation
Ensures compatibility with a wide range of laser drivers
For SONET and OTN transfer rates; seamless shift between rates
Small physical form factor simplifies design and helps reduce
board space
Ensures seamless support for multiple line speeds without using
external components
Ensures interoperability between SerDes chips and framer
Ensures alignment of data and clock signals coming from
the framer
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