FW82546GB Intel, FW82546GB Datasheet - Page 15

• Manufacturer Part Number: FW82546GB
• Manufacturer: Intel

Specifications of FW82546GB

• Operating Supply Voltage (typ): 1.5/2.5/3.3V
• Operating Supply Voltage (min): 1.43/2.38/3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 364
• Lead Free Status / RoHS Status: Not Compliant

3.2.1
Datasheet
PCI Address, Data and Control Signals
AD[63:0]
CBE[7:0]#
PAR
PAR64
FRAME#
IRDY#
TRDY#
Symbol
TS
TS
TS
TS
STS
STS
STS
Type
Address and Data. Address and data signals are multiplexed on the same PCI pins. A
bus transaction includes an address phase followed by one or more data phases.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
low. During the address phase AD[63:0] contain a physical address (64 bits). For I/O,
this is a byte address, and for configuration and memory, a DWORD address. The
82546GB device uses little endian byte ordering.
During data phases, AD[7:0] contain the least significant byte (LSB) and AD[63:56]
contain the most significant byte (MSB).
The 82546GBcontroller may optionally be connected to a 32-bit PCI bus. On the 32-bit
bus, AD[63:32] and other signals corresponding to the high order byte lanes do not
participate in the bus cycle.
Bus Command and Byte Enables. Bus command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
CBE[7:0]# define the bus command. In the data phase, CBE[7:0]# are used as byte
enables. The byte enables are valid for the entire data phase and determine which byte
lanes contain meaningful data.
CBE0# applies to byte 0 (LSB) and CBE7# applies to byte 7 (MSB).
Parity. The Parity signal is issued to implement even parity across AD[31:0] and
CBE[3:0]#. PAR is stable and valid one clock after the address phase. During data
phases, PAR is stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains
valid until one clock after the completion of the current data phase.
When the 82546GB controller is a bus master, it drives PAR for address and write data
phases, and as a slave device, drives PAR for read data phases.
Parity 64. The Parity 64 signal is issued to implement even parity across AD[63:32]
and CBE[7:4]#. PAR64 is stable and valid one clock after the address phase. During
data phases, PAR64 is stable and valid one clock after either IRDY# is asserted on a
write transaction or TRDY# is asserted after a read transaction. Once PAR64 is valid, it
remains valid until one clock after the completion of the current data phase.
When the 82546GB controller is a bus master, it drives PAR64 for address and write
data phases, and as a slave device, drives PAR64 for read data phases.
Cycle Frame.
beginning and length of an access and indicate the beginning of a bus transaction.
While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the
transaction is in the final data phas
Initiator Ready. Initiator Ready indicates the ability of the 82546GB controller (as bus
master device) to complete the current data phase of the transaction. IRDY# is used in
conjunction with the Target Ready signal (TRDY#). The data phase is completed on
any clock when both IRDY# and TRDY# are asserted.
During the write cycle, IRDY# indicates that valid data is present on AD[63:0]. For a
read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together. The 82546GB controller drives IRDY#
when acting as a master and samples it when acting as a slave.
Target Ready. The Target Ready signal indicates the ability of the 82546GB controller
(as a selected device) to complete the current data phase of the transaction. TRDY# is
used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed
on any clock when both TRDY# and IRDY# are sampled asserted.
During a read cycle, TRDY# indicates that valid data is present on AD[63:0]. For a write
cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together. The 82546GB device drives TRDY# when
acting as a slave and samples it when acting as a master.
The Frame signal is driven by the
Name and Function
e.
Networking Silicon — 82546GB
82546GB device to indicate the
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