LU82551ER Intel, LU82551ER Datasheet - Page 2

• Manufacturer Part Number: LU82551ER
• Manufacturer: Intel

Specifications of LU82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

Revision History
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The 82551ER may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
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Revision
Sept 2007
Sept 2007
Sept 2008
Sep 2004
Nov 2004
Nov 2004
Nov 2008
Jan 2002
Apr 2002
Mar 2003
Jan 2005
Oct 2006
Mar 2008
Date
Revision
1.0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
• Added description for No Connect pins and corrected typographical errors.
• Clarified EEPROM address map and word definitions for the 82551ER.
• Added more detailed information for I
Changed document status to Intel Confidential.
• Removed document status.
• Removed references to MDI/MDI-X feature, not supported by the 82551ER.
• Added references to the MDI/MDI-X feature.
• Added lead-free information.
• Removed EEPROM Map bit descriptions. These descriptions can now be found in the
• Added 82551ER Test Port Functionality (Chapter 10).
• Added new values for RBIAS100 and RBIAS10. RBIAS100 = 649 and RBIAS10 = 619 .
• Removed all references to the 82551IT and 82551QM controllers. 82551IT and 82551QM
• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer
• Updated the section describing “Multiple Priority Transmit Queues”.
• Updated the section describing “VLAN Support”.
• Added statement that no changes to existing soldering processes are needed for the 2-layer
• Added a note for PHY signals RBIAS100 and RBIAS10 to Table 8.
• Added Figure 28 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and
• Added Section 13 “Reference Schematics”, updated Section 11.1 (changed Tcase to ambient)
• Updated Figures 31 and 32. Added Digital I/O and Crystal Input One (X1) Characteristics
• Updated Figure 32: changed TEST pull down resistor value (62 K to 1 K).
• Updated section 1.4 (changed A0 stepping to A1).
• Updated Table 12 (changed words 30h:33h to reserved).
• Updated Table 8 (X1 and X2 pin descriptions).
• Updated Tables 52 and 53 (Digital I/O and crystal input one (X1) characteristics).
82551QM/ER/IT EEPROM Map and Programming Information.
information can now be found in their respective datasheets.
0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information.
0.32 mm wide-trace substrate change in the section describing “Package Information”.
metal diameter dimensions.
and added ordering information to Section 1.4.
(Tables 52 and 53). Updated Section 5.6.4.
CC
Description
in the DC specifications table.
Datasheet