TS81102G0VTP E2V, TS81102G0VTP Datasheet
TS81102G0VTP
Specifications of TS81102G0VTP
Related parts for TS81102G0VTP
TS81102G0VTP Summary of contents
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Features • Programmable DMUX Ratio: – 1:4: Data Rate Max = 1 Gsps – PD (8b/10b) < 4.3/4.7 W (ECL 50 output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50 output) – ...
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Block Diagram Figure 1. Block Diagram Data Path FS/8 BIST 8/10 mux 8/10 even odd master master latch latch odd even slave slave latch latch 8/10 Even Ports TS81102G0 2 delay NAP B 2 mux Phase control ClkPar (8 stage ...
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Internal Timing This diagram corresponds to an established operation of the DMUX with Synchronous Reset. Diagram Figure 2. Internal Timing Diagram 500 ps min Data In N N Fs/2 = ClkPar Master ...
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Functional The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology fea- turing a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be Description processed at the DMUX ...
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Main Function Description Programmable The conversion ratio is programmable: 1:4 or 1:8. DMUX Ratio Figure 3. Programmable DMUX Ratio Parallel Output Figure 4. Parallel Mode Mode Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL) The input clock phase can be adjusted with ...
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Asynchronous Figure 5. Asynchronous Reset Reset (ASYNCRESET) The Asynchronous Reset is a master reset of the port selection, which works on TTL levels active on the high level. During an asynchronous reset, the clock must ...
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Counter When the counter is reset, its initial states depends on the conversion ratio: Programmable • 1:8: counting on 8 bits, State • 1:4: counting on 4 bits. Pipeline Delay The maximum pipeline delay depends on the conversion ratio: • ...
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Single-ended To reduce the pin number and power consumption of the DMUX, the eight output ports are Output Data single-ended. To reach the high frequency output (up to 250 MHz) with a reasonable power consumption, the swing must be limited ...
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Differential Data The front edge of the DataReady output occurs when data is available on the corresponding Ready Output port. The frequency of this clock depends on the conversion ratio (1:8 or 1:4), with a duty cycle of 50%. The ...
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Table 2. Absolute Maximum Ratings (Continued) Parameter Data output current TTL input voltage Maximum input voltage on diode for temperature measurement Maximum input current on diode Maximum junction temperature Storage temperature Note: Absolute maximum ratings are limiting values ...
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Electrical Tj (typical Full Temperature Range: -40 C < Tc; Tj < 110 C. Operating (Guaranteed temperature range are depending on part number) Characteristics Table 4. Electrical Specifications Parameter Power Requirements Positive supply voltage Negative supply voltage ...
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Table 4. Electrical Specifications (Continued) Parameter PECL (50 ) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits TTL (75 ) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits Delay Adjust Control DMUXDelAdjCtrl ...
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Table 4. Electrical Specifications (Continued) Parameter Output level drift with temperature (reference outputs) Digital Inputs ECL Input Voltages Logic “0” voltage Logic “1” voltage TTL Input Voltages Logic “0” voltage Logic “1” voltage Note: 1. The supply current I PLUSD ...
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Table 5. Switching Performances (Continued) Parameter Synchronous Reset Setup time from SyncReset to Clkln DR input clock DR/2 input clock Hold time from Clkln to SyncReset DR input clock DR/2 input clock Rise/fall for (10% – 90%) Input Data Setup ...
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Table 5. Switching Performances (Continued) Parameter Setup time from Bist to Clkln Rise/fall time for (10% – 90%) ADC Delay Adjust Input frequency Input pulse width (high) Input pulse width (low) Input rise/fall time Output rise/fall time Data output delay ...
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Input Clock Timings Figure 10. Input Clock TC2 TFCKIN TC1 TRCKIN Clkln TSCKIN Data [0.. Clkln Type = 1 DataReady Mode (DR) ADC Delay Adjust Timing Diagram Figure 11. ADC Delay Adjust Timing Diagram TC2ADA TFIADA TC1ADA TRIADA ...
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Timing Diagrams with With a nominal tuning of DMUXDelAdj at a frequency of 2 GHz, d1 and d2 data is lost because Asynchronous Reset of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain ...
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With a nominal tuning of DMUXDelAdj GHz (1:4 mode) d1 data is lost because of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is used to obtain good setup and hold times ...
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Timing Diagrams with Following is an example of the Synchronous Reset’s utility in case of de-synchronization of the Synchronous Reset DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < ...
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Figure 17. Synchronous Reset, 1:4 Ratio, DR Mode SyncReset Internal Port Selection (not available out of the DEMUX) A[0..9] B[0..9] C[0..9] D[0..9] Example of Synchronous Reset’s utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event ...
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Figure 19. Synchronous Reset, 1:4 ratio, DR/2 Mode SyncReset Clkn I[0..9] Internal Port Selection (not available out of the DEMUX) A[0..9] B[0..9] C[0..9] D[0..9] DR Note: In case of low clock frequency and start with asynchronous reset, only the first ...
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Explanation of Test Levels Table 6. Explanation of Test Levels Num Notes: TS81102G0 22 Characteristics 1 100% production tested at + 100% production tested at +25 C, and sample tested at specified temperatures. 3 Sample tested only at ...
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Package Description Pin Description Table 7. TS81102G0 Pin Description Type Name Digital Inputs I[0…9] Clkln Outputs A[0…9] H[0…9] DR RefA RefH Control Signals ClklnType RatioSel Bist SwiAdj Diode NbBit Synchronization AsyncReset SyncReset DMUXDelAdjCtrl ADCDelAdjCtrl ADCDelAdjln ADCDelAdjOut Power Supplies GND V ...
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TBGA 240 Package – Pinout Row Col Name Row Col ...
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Figure 20. TBGA 240 Package: Bottom View RstSyncb Demuxdeladjctrcl A8 A6 RstSync Demuxdeladjctrclb Asyncreset GND GND GND DIODE VPLUSD I0 I0b GND VCC VCC I1b I1 VEE VEE I2b GND GND I2 I3 ...
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Outline Dimensions Figure 21. Package Dimension – 240 Tape Ball Grid Array 0. Corner 45 degree 0.5 mm chamfer (4 PLCS) Top View Detail A Side View P aaa C Detail A 5 Thermal and ...
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Thermal Resistance A pin-fin type heat sink of a size can be used to reduce thermal resis- from Junction to tance. This heat sink should not be glued to the top of ...
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Temperature Diode The theoretical characteristic of the diode according to the temperature when Characteristic depicted below. Figure 23. Temperature Diode Characteristic Moisture This device is sensitive to moisture (MSL3 according to the JEDEC standard). Characteristic ...
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Detailled Cross The following diagram depicts a detailed cross section of the DMUX TBGA package. Section Figure 24. TBGA 240: 1/2 Cross Section Die Attach Epoxy/Ag Silicon Die Block Epoxy resin encapsulant In the DMUX package shown above, the die’s ...
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Applying the The TSEV81102G0 DMUX evaluation board is designed to be connected with the TSEV8388G and TSEV83102G0 ADC evaluation boards. TS81102G0 DMUX Figure 25. TSEV81102G0 DMUX Evaluation Boards Analog Input 10bits 2 GHz TS83102G0 Please refer to the "ADC and ...
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ADC to DMUX The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC. Connections The die in the TBGA package is up. For the ADC, different types of packages can be used such as CBGA with ...
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TSEV81102G0TP: Device Evaluation Board General The TSEV81102G0TP DMUX Evaluation Board (EB) is designed to simplify the characteriza- tion and the evaluation of the TS81102G0 device (2 Gsps DMUX). The DMUX EB enables Description testing of all the DMUX functions: Synchronous ...
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... Ordering Information Table 9. Ordering Information Part Number Package JTS81102G0-1V1A Die TS81102G0CTP TBGA 240 TS81102G0VTP TBGA 240 TSEV81102G0TPZR3 TBGA 240 Datasheet Status Table 10. Datasheet Status Description Datasheet Status Objective specification Target specification Preliminary specification -site Preliminary specification -site Product specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134) ...
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Addendum This section has been added to the description of the device for better understanding of the synchronous reset operation. It puts particular stress on the setup and hold times defined in the switching characteristics table (Table 5), linked with ...
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Figure 27. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – TIMINGS Fs Time Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If ...
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Operation in DR/2 In DR/2 mode, the DMUX input clock can run GHz in 1:8 ratio or 500 MHz in 1:4 Mode ratio, since the DR/2 clock from the ADC is half the sampling frequency. Both ...
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Figure 33. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full-speed) – Timings Fs/2 Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the ...
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