CYW15G0401DXB-BGXI Cypress Semiconductor Corp, CYW15G0401DXB-BGXI Datasheet
CYW15G0401DXB-BGXI
Specifications of CYW15G0401DXB-BGXI
Related parts for CYW15G0401DXB-BGXI
CYW15G0401DXB-BGXI Summary of contents
Page 1
... Note: 1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0401DXB refers to OBSAI RP3 compliant devices (maximum operating data rate is 1540 MBaud). CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0401DXB refers to all three devices. ...
Page 2
... The CYW15G0401DXB operates from 195 to 1540 MBaud, which includes operation at the OBSAI RP3 datarate of both 1536 MBaud and 768 MBaud. The CYV15G0401DXB satisfies the SMPTE 259M and SMPTE 292M compliance as per the EG34-1999 Pathological Test Requirements. The multiple channels in each device may be combined to allow transport of wide buses across significant distances with minimal concern for offsets in clock phase or link delay ...
Page 3
... Document #: 38-02002 Rev. *L x10 x11 Phase Elasticity Elasticity Align Buffer Buffer Decoder Encoder 8B/10B 8B/10B Framer Serializer Deserializer Deserializer CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB x10 x11 x11 Phase Elasticity Align Buffer Buffer Buffer Decoder Encoder Decoder 8B/10B 8B/10B 8B/10B Framer Framer Serializer Deserializer RX RX ...
Page 4
... TXRST PARCTL Document #: 38-02002 Rev. *L Bit-rate Clock BIST Enable Latch Transmit Mode CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB = Internal Signal Character-Rate Clock BISTLE BOE[7:0] RBIST[D:A] Output Enable OELE Latch 8 10 OUTA1+ OUTA1– OUTA2+ OUTA2– TXLBA 10 OUTB1+ OUTB1– OUTB2+ OUTB2– TXLBB ...
Page 5
... IND2+ Clock & IND2– Data Recovery TXLBD PLL RBIST[D:A] FRAMCHAR RXRATE RFEN RFMODE RXCKSEL DECMODE 2 RXMODE[1:0] Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB = Internal Signal TRSTZ TMS JTAG TCLK Boundary Scan TDI Controller TDO LFIA 8 RXDA[7:0] RXOPA 3 RXSTA[2:0] RXCLKA+ Clock ÷2 Select RXCLKA– ...
Page 6
... REF BOND GND [0] [2] ST[0] CLK+ ST[1] RXSTD GND TXCLK TXRST TXOPA SCSEL GND [1] O- RXDD GND TXCLK N/C TXCLK TXPER GND [ CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB INA2- OUT V INB1- OUT INB2- OUT CC A2- B1- B2- INA2+ OUT V INB1+ OUT INB2+ OUT CC A2+ B1+ ...
Page 7
... GND RXSTD ST[1] CLK+ ST[0] [2] [0] GND SCSEL TXOP TXRST TXCLK GND RXSTD A O- [1] GND TXPER TXCLK N/C TXCLK GND RXDD [0] CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB IND1- V OUT INC2- OUT INC1- CC C2- C1- B IND1+ V OUT INC2+ OUT INC1+ CC C2+ C1+ C PAR V INSELB INSELC ...
Page 8
... Table 2 for details. Special Character Select. Used in some transmit modes along with TXCTx[1:0] to encode special characters or to initiate a Word Sync Sequence. When the transmit paths are configured for independent input clocks (TXCKSEL = MID), SCSEL is captured relative to TXCLKA↑. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 9
... TXCLKO±, but may be offset in phase. The internal operating phase of each input clock (relative to REFLCK or TXCLKO±) is adjusted when TXRST = LOW and locked when TXRST = HIGH. (ground). The HIGH level is usually implemented by direct connection CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB [4] is used as the . When CC Page [+] Feedback ...
Page 10
... RFMODE and selected framing character as selected by FRAMCHAR. Receive Operating Mode. These inputs are interpreted to select one of nine operating modes of the receive path. See Table 14 for details. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 11
... RXCLKA± and RXCLKC± output the recovered clock from receive channel selected by RXCLKB+ and RXCLKD+. This output clock may operate at the character-rate or half the character-rate as selected by RXRATE. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB th the serial bit-rate) or character Page [+] Feedback ...
Page 12
... Serial Rate Select. This input specifies the operating bit-rate range of both transmit and receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud (800–1540 MBaud for CYW15G0401DXB). When SPDSEL is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid. ...
Page 13
... The specific mapping of BOE[7:0] signals to transmit output enables is listed in Table 10. When OELE returns LOW, the last values present on BOE[7:0] are captured in the internal Output Enable Latch. If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable all outputs. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 14
... K28.5 immediately following the next framing character received 10—Delete next framing character received 11—Normal data. These outputs are driven only when the device is configured as a master, all four channels are bonded together, and the receive parallel interface is clocked by REFCLK↑. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 15
... SCSEL input is sampled synchronous to TXCLKA↑. While the value on SCSEL still affects all channels interpreted when the character containing it is read from the transmit Phase-align Buffer (where all four paths are inter- nally clocked synchronously). CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 16
... C0.7 character of proper disparity to be passed to the Transmit Shifter. When the Encoder is bypassed (TXMODE[1] = LOW, LOW), detection of a parity error causes a positive disparity version of a C0.7 transmission character to be passed to the Transmit Shifter. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB [7] [8] MID TXMODE[1] TXMODE[1] ≠ LOW ...
Page 17
... TX Modes 1 and 2—Factory Test Modes These modes enable specific factory test configurations. They are not considered normal operating modes of the device. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Operating Mode SCSEL Control TXCTx Function None Encoder Bypass ...
Page 18
... When configured in TX Mode 4, the SCSEL input is captured along with the associated TXCTx[1:0] data control inputs. These bits combine to control the interpretation of the TXDx[7:0] bits and the characters generated by them. These bits are interpreted as listed in Table 6. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB [4] are clocked by REFCLK. When ...
Page 19
... TX Mode 3Two additional encoding maps are provided for use when receive channel bonding is enabled. When Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB dual-channel bonding is enabled (RXMODE[1] = MID), the CYP(V)(W)15G0401DXB is configured such that channels A and B are bonded together to form a two-character-wide path, and channels C and D are bonded together to form a second two-character-wide path ...
Page 20
... Encoded data character on channel K28.5 fill character on channel Special character code on channel 16-character word sync on channel Encoded data character on channel K28.5 fill character on channel Special character code on channel 16-character word sync on channel 16-character word sync on channels and D CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 21
... This clock multiplier PLL can accept a REFCLK input between 20 MHz and 150 MHz (19.5 MHz CYW15G0401DXB), however, this clock range is limited by the operating mode of the CYP(V)(W)15G0401DXB clock Document #: 38-02002 Rev. *L multiplier (controlled by TXRATE) and by the level on the SPDSEL input. Logic) ...
Page 22
... Any disabled channel indicates an asserted LFIx output. When RXLE returns LOW, the values present on the BOE[7:0] inputs are latched in the Receive Channel Enable Latch, and remain there until RXLE returns HIGH to open the latch again. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB [14] Page [+] Feedback ...
Page 23
... PLL-based clock distribution elements. In this framing mode, the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits, with both instances on identical 10-bit character boundaries. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Bits Detected in Framer Bits Detected Reserved for test [15] 00111110XX or 11000001XX ...
Page 24
... Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB These generators are enabled by the associated BOE[x] signals listed in Table 10 (when the BISTLE latch enable input is HIGH). When enabled, a register in the associated receive channel becomes a pattern generator and checker by logically converting to a Linear Feedback Shift Register (LFSR) ...
Page 25
... Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB how the transmitter sends its data. Insertion of a K28.5 character can only occur when the receiver has a framing character in the Elasticity Buffer. Likewise, to delete a framing character, one must also be present in the Elasticity Buffer. To ...
Page 26
... BONDST[1:0] status. This selection is made using the RXCLKB+ and RXCLKD+ inputs, as shown in Table 15. This allows the master channel selection to be changed through external control of the MASTER, RXCLKB+, [17] and RXCLKD+ inputs. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 27
... The RXOPx outputs are also driven from the associated Output Register, but their interpretation is under the separate control of PARCTL. Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB inputs while the OELE and RXLE signals are raised and lowered. For systems that do not require dynamic control of power, or want the device to power fixed configuration also possible to strap the RXLE and OELE control signals HIGH to permanently enable their associated latches ...
Page 28
... Machine, and are listed in Table 20. The receive status when the channels are operated independently with channel bonding disabled is shown in Table 23. The receive status when Receive BIST is enabled is shown in Table 24. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Receive Parity Generate Mode (PARCTL) MID LOW DECMODE DECMODE [19] ≠ ...
Page 29
... Resync. The receiver state machine is in the Resynchronization state. In this state the data on the output bus reflects the presently decoded FRAMCHAR. Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Status Type-A Receive State Machine This machine has four primary states: NO_SYNC, RESYNC, COULD_NOT_BOND, and IN_SYNC, as shown in Figure 2. The IN_SYNC state can respond with multiple status types, while others can respond with only one type ...
Page 30
... Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR (Invalid Minus Valid = 4) 6 Valid Character other than a FRAMCHAR Figure 2. Status Type-A Receive State Machine for Channel Bonding Document #: 38-02002 Rev. *L NO_SYNC 5 RXSTx=101 RESYNC 1 RXSTx=111 State Transition Conditions CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Reset 4 2 Page [+] Feedback ...
Page 31
... FRAMCHAR Before a Valid Character) AND (Bonded to MASTER Channel) 7 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) Figure 3. Status Type-B Receive State Machine for Channel Bonding Document #: 38-02002 Rev. *L RXSTx = 101 5 RXSTx = 010 6 7 RXSTx = 101 Condition CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Reset NO_SYNC 4 3 RESYNC RXSTx=111 2 Page [+] Feedback ...
Page 32
... BIST Error. While comparing characters, a mismatch was found in one or more of the decoded character bits. 111 3 BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to enable the LFSR. Document #: 38-02002 Rev. *L Type-A Status INVALID Receive BIST Status (Receive BIST = Enabled) CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Type-B status Page [+] Feedback ...
Page 33
... To ensure compatibility between the source and destination systems when operating in BIST modes, the sending and Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB receiving ends of the link must use the same receive clock setup. (RXCKSEL = MID or RXCKSEL ≠ MID). JTAG Support The CYP(V)(W)15G0401DXB contains a JTAG port to allow system level diagnosis of device interconnect ...
Page 34
... Yes Buffer Error No Compare Next Character BIST_COMMAND_COMPARE (001) Match Command Data or Command Data End-of-BIST State Yes, RXSTx = BIST_LAST_GOOD (010) No, RXSTx = Figure 2. Receive BIST State Machine CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Receive BIST Detected LOW RX PLL Out of Lock RXSTx = RXSTx = BIST_DATA_COMPARE (000) No Page [+] Feedback ...
Page 35
... IN Min. ≤ V ≤ Max. CC Min. ≤ V ≤ Max. CC Min. ≤ V ≤ Max GND IN 100Ω differential load 150Ω differential load CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB V CC +3.3V ±5% +3.3V ±5% Min. Max. Unit 2 0.4 V –20 –100 mA µA – –0.5 0 ...
Page 36
... The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses the threshold voltage. 30. This parameter is 154 MHz for CYW15G0401DXB 31. This parameter is 6.49 ns for CYW15G0401DXB 32. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. ...
Page 37
... LOW) could be used to clock the receive data out of the device. Document #: 38-02002 Rev. *L Over the Operating Range (continued) Description and t parameters. This means that at faster character rates the REFCLK duty cycle REFH REFL CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Min. Max. Unit 0.2 1.7 ns 0.2 1 ...
Page 38
... INPECL Notes: 38. This parameter is 649 ps for CYW15G0401DXB 39. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range. 40. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range. 41. Total jitter is calculated at an assumed BER of 1E – ...
Page 39
... The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input. Document #: 38-02002 Rev TXCLK t TXCLKH TXCLKL t TXDS t REFCLK t REFL t TREFDS t t REFCLK t REFH Note 44 t TREFDS t REFCLK t REFH t TXCLKO t TXCLKOD– Note 45 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB t TXDH TREFDH t REFL t TREFDS t TREFDH t REFL Page [+] Feedback ...
Page 40
... Note 45 t TXCLKO t TXCLKOD– HOTLink II Receiver t REFCLK t t REFH REFL t RREFDA t REFADV+ t REFCDV+ Note 47 t REFCLK t REFH t RREFDA t RREFDV t REFADV+ t REFCDV+ Note 47 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB (continued) t RREFDV t REFADV– t REFCDV– t REFL t RREFDA t RREFDV t REFADV– t REFCDV– Note 48 Page [+] Feedback ...
Page 41
... RXDx[7:0], RXSTx[2:0], RXOPx Receive Interface Read Timing RXCKSEL = HIGH or MID RXRATE = HIGH RXCLKx+ – RXCLKx RXDx[7:0], RXSTx[2:0], RXOPx Document #: 38-02002 Rev. *L HOTLink II Receiver t RXCLKP t RXCLKH RXCLKL t RXDV– t RXCLKP t RXCLKH t RXDV– CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB (continued) t RXDV+ t RXCLKL t RXDV+ Page [+] Feedback ...
Page 42
... VCC POWER E02 VCC POWER E03 VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Ball ID Signal Name Signal Type E19 VCC POWER E20 VCC POWER F01 TXPERC LVTTL OUT F02 TXOPC LVTTL IN PU F03 TXDC[0] ...
Page 43
... V15 TXDA[7] LVTTL IN V16 VCC POWER V17 RXDA[7] LVTTL OUT V18 RXDA[3] LVTTL OUT V19 RXDA[0] LVTTL OUT CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Ball ID Signal Name Signal Type V20 RXSTA[0] LVTTL OUT W01 TXDD[5] LVTTL IN W02 TXDD[7] LVTTL IN W03 LFID LVTTL OUT W04 RXCLKD– ...
Page 44
... When c is set the decimal value of the binary number Document #: 38-02002 Rev. *L CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB composed of the bits and A in that order, and the y is the decimal value of the binary number composed of the bits H, G, and F in that order. When c is set and y are ...
Page 45
... Character in which the error occurred. Table 27 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 . ...
Page 46
... D29.1 001 11101 100001 1011 D30.1 001 11110 010100 1011 D31.1 001 11111 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001 ...
Page 47
... D30.3 011 11110 010100 0101 D31.3 011 11111 011000 1101 D0.5 101 00000 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0011 011000 1100 011101 0011 100010 1100 101101 0011 010010 1100 110001 1100 ...
Page 48
... D29.5 101 11101 100001 1101 D30.5 101 11110 010100 1101 D31.5 101 11111 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Current RD− Current RD+ abcdei fghj abcdei fghj 011101 1010 100010 1010 101101 1010 010010 1010 110001 1010 110001 1010 110101 1010 ...
Page 49
... D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0001 011000 1110 011101 0001 100010 1110 101101 0001 010010 1110 110001 1110 ...
Page 50
... C1.7 (CE1) 111 00001 [60] C2.7 (CE2) 111 00010 [60] C4.7 (CE4) 111 00100 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB [49, 50] Current RD− Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011 110000 1100 001111 0010 ...
Page 51
... CYW15G0401DXB-BGI Standard CYP15G0401DXB-BGXC Standard CYP15G0401DXB-BGXI Standard CYV15G0401DXB-BGXC Standard CYV15G0401DXB-BGXI OBSAI CYW15G0401DXB-BGXC OBSAI CYW15G0401DXB-BGXI Package Diagram 256-Lead L2 Ball Grid Array ( 1.57 mm) BL256 TOP VIEW 27.00±0.13 A1 CORNER I.D. 1.57±0.175 0.97 REF. 0.60±0.10 C SEATING PLANE SIDE VIEW HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. CPRI is a trademark of Siemens AG ...
Page 52
... Added Power-up Requirements Changed CYP15G0401DXB to CYP(V)15G0401DXB to abbreviate title. Type corre- sponding to the Video compliant parts Reduced the lower limit of the serial signaling rate from 200 Mbaud to 195 Mbaud and changed the associated specifications accordingly Added CYPV15G0401DXB to title CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Page [+] Feedback ...
Page 53
... Revised Typical Power numbers to match final characterization data. Minor change: package diagram disappeared from online pdf Added CYW15G0401DXB part number for OBSAI RP3 compliance to support operating data rate upto 1540 MBaud. Made changes to reflect OBSAI RP3 and CPR compliance. Added Pb-free package option for all parts listed in the datasheet. ...