CYP15G0401TB-BGXI Cypress Semiconductor Corp, CYP15G0401TB-BGXI Datasheet

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... HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, command, and BIST) with other HOTLink devices. The transmitters (TX) of the CYP15G0401TB Quad HOTLink II consist of four byte-wide channels. Each channel can accept either eight-bit data characters or pre-encoded 10-bit transmission characters ...

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... Each transmitter contains an independent BIST pattern generator. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit section, and across the interconnecting links. CYP15G0401TB Transmitter Logic Block Diagram x10 Phase Align Buffer Encoder ...

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... PARCTL Document #: 38-02112 Rev. ** PRELIMINARY Bit-rate Clock BIST Enable Latch Transmit Mode Boundary Controller CYP15G0401TB TRSTZ BISTLE BOE[7:0] Output Enable OELE Latch 8 10 OUTA1+ OUTA1– OUTA2+ OUTA2– 10 OUTB1+ OUTB1– OUTB2+ OUTB2– 10 OUTC1+ OUTC1– OUTC2+ OUTC2– ...

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... TXDA GND CLK- [1] N/C GND N/C N/C REF N/C GND CLK+ N/C GND TXCLK TXRST TXOPA SCSEL GND O- N/C GND TXCLK N/C TXCLK TXPER GND CYP15G0401TB N/C OUT V N/C OUT N/C OUT CC A2- B1- B2- GND OUT V V OUT GND OUT CC CC ...

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... GND TXDA REF N/C N/C GND N/C [1] CLK- GND N/C REF N/C N/C GND N/C CLK+ GND SCSEL TXOP TXRST TXCLK GND N GND TXPER TXCLK N/C TXCLK GND N CYP15G0401TB N/C V OUT N/C OUT N/C CC C2- C1 OUT V OUT C2+ C1+ PAR TMS TDI ...

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... Pin Descriptions CYP15G0401TB Quad HOTLink II Transmitter Pin Name I/O Characteristics Transmit Path Data Signals TXPERA LVTTL Output, changes [2] TXPERB relative to REFCLK↑ TXPERC TXPERD TXCTA[1:0] LVTTL Input, TXCTB[1:0] synchronous, TXCTC[1:0] sampled by the TXCTD[1:0] selected TXCLKx↑ or [2] REFCLK↑ TXDA[7:0] LVTTL Input, ...

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... Pin Descriptions (continued) CYP15G0401TB Quad HOTLink II Transmitter Pin Name I/O Characteristics TXRST LVTTL Input, asynchronous, internal pull-up, sampled by [2] REFCLK↑ Transmit Path Clock and Clock Control [3] TXCKSEL Three-level Select , static control input TXCLKO± LVTTL Output TXRATE LVTTL Input, static control input, ...

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... Pin Descriptions (continued) CYP15G0401TB Quad HOTLink II Transmitter Pin Name I/O Characteristics Device Control Signals [3] PARCTL Three-level Select , static control input [3] SPDSEL Three-level Select static control input TRSTZ LVTTL Input, internal pull-up REFCLK± Differential LVPECL or single-ended LVTTL Input Clock Analog I/O and Control OUTA1± ...

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... This device supports four single-byte or single-character channels. CYP15G0401TB Transmit Data Path Operating Modes The transmit path of the CYP15G0401TB supports four character-wide data paths. These data paths are used in multiple operating modes as controlled by the TXMODE[1:0] inputs. Input Register ...

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... In addition to the ten data and control bits that are captured at each transmit Input Register, a TXOPx input is also available on each channel. This allows the CYP15G0401TB to support ODD parity checking for each channel. Parity checking is available for all operating modes (including Encoder Bypass). ...

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... Many of the Special Character codes listed in Table 14 may be generated by more than one input character. The CYP15G0401TB is designed to support two independent (but non-overlapping) Special Character code tables. This allows the CYP15G0401TB to operate in mixed environments with other Cypress HOTLink devices using the enhanced Cypress command code set, and the reduced command sets of other non-Cypress devices ...

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... TXCTx[1:0] inputs must both be sampled HIGH. The gener- ation and operation of this Word Sync Sequence is the same as TX Mode 3. Transmit BIST Each transmit channel contains an internal pattern generator that can be used to validate both device and link operation. CYP15G0401TB [2] clocked by REFCLK. When ...

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... This clock multiplier PLL can accept a REFCLK input between 20 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYP15G0401TB clock multiplier (controlled by TXRATE) and by the level on the SPDSEL input. When TXRATE = HIGH (Half-rate REFCLK), TXCKSEL = HIGH or MID (TXCLKx or TXCLKA selected to clock input register invalid mode of operation ...

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... Output Enable Latch. Document #: 38-02112 Rev. ** PRELIMINARY Device Reset State When the CYP15G0401TB is reset by assertion of TRSTZ, the Transmit Enable Latches are cleared, and the BIST Enable Latch is preset. In this state, all transmit channels are disabled, and BIST is disabled on all channels. Following a device reset necessary to enable the transmit channels used for normal operation ...

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... Document #: 38-02112 Rev. ** PRELIMINARY Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYP15G0401TB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up Operating Range + 0.5V CC Range ...

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... LVTTL Output Test Load 3.0V 2.0V 2. 1.4V th 0.8V 0.8V GND ≤ (c) LVTTL Input Test Waveform CYP15G0401TB AC Characteristics Parameter CYP15G0401TB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKx Clock Frequency TS t TXCLKx Period TXCLK [16] t TXCLKx HIGH Time TXCLKH [16] t TXCLKx LOW Time ...

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... REFCLK Fall Time (20% – 80%) REFF Transmit Data Setup Time to REFCLK (TXCKSEL = LOW) t TREFDS Transmit Data Hold Time from REFCLK (TXCKSEL = LOW) t TREFDH CYP15G0401TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range Parameter Description t Bit Time B [16] t CML Output Rise Time 20% – 80% (CML Test ...

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... CYP15G0401TB HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing TXCKSEL ≠ LOW t TXCLKx TXDx[7:0], TXCTx[1:0], TXOPx, SCSEL Transmit Interface Write Timing TXCKSEL = LOW TXRATE = LOW t REFH REFCLK TXDx[7:0], TXCTx[1:0], TXOPx, SCSEL Transmit Interface Write Timing TXCKSEL = LOW TXRATE = HIGH Note 25 REFCLK ...

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... CYP15G0401TB HOTLink II Transmitter Switching Waveforms Transmit Interface TXCLKO Timing TXCKSEL = LOW t TXRATE = LOW REFCLK t Note 27 TXCLKOD+ TXCLKO Document #: 38-02112 Rev. ** PRELIMINARY t REFCLK t REFH REFL Note 26 t TXCLKO t TXCLKOD– CYP15G0401TB (continued) Page [+] Feedback ...

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... NO CONNECT E01 VCC POWER E02 VCC POWER E03 VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER CYP15G0401TB Ball ID Signal Name Signal Type E19 VCC POWER E20 VCC POWER F01 TXPERC LVTTL OUT F02 TXOPC LVTTL IN PU F03 TXDC[0] ...

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... GND GROUND V14 TXDA[3] LVTTL IN V15 TXDA[7] LVTTL IN V16 VCC POWER V17 N/C NO CONNECT V18 N/C NO CONNECT V19 N/C NO CONNECT CYP15G0401TB Ball ID Signal Name Signal Type V20 N/C NO CONNECT W01 TXDD[5] LVTTL IN W02 TXDD[7] LVTTL IN W03 N/C NO CONNECT W04 N/C NO CONNECT ...

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... After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Trans- CYP15G0401TB the validity of received ...

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... Transmission Character in which the error occurred. Table 11 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0401TB Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 ...

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... D28.1 001 11100 010001 1011 D29.1 001 11101 100001 1011 D30.1 001 11110 010100 1011 D31.1 001 11111 CYP15G0401TB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001 ...

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... D29.3 011 11101 100001 0101 D30.3 011 11110 010100 0101 D31.3 011 11111 011000 1101 D0.5 101 00000 CYP15G0401TB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0011 011000 1100 011101 0011 100010 1100 101101 0011 010010 1100 110001 1100 ...

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... D28.5 101 11100 010001 1101 D29.5 101 11101 100001 1101 D30.5 101 11110 010100 1101 D31.5 101 11111 CYP15G0401TB Current RD− Current RD+ abcdei fghj abcdei fghj 011101 1010 100010 1010 101101 1010 010010 1010 110001 1010 110001 1010 110101 1010 ...

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... D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0401TB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0001 011000 1110 011101 0001 100010 1110 101101 0001 010010 1110 110001 1110 ...

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... C1.7 (CE1) 111 00001 [39] C2.7 (CE2) 111 00010 [39] C4.7 (CE4) 111 00100 CYP15G0401TB [28, 29] Current RD− Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011 110000 1100 001111 0010 ...

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... Ordering Information Speed Ordering Code Package Name Standard CYP15G0401TB-BGC Standard CYP15G0401TB-BGI Standard CYP15G0401TB-BGXC Standard CYP15G0401TB-BGXI Package Diagram 256-Lead L2 Ball Grid Array ( 1.57 mm) BL256 TOP VIEW 27.00±0.13 A1 CORNER I.D. 1.57±0.175 0.97 REF. 0.60±0.10 C SEATING PLANE SIDE VIEW HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines ...

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... Document History Page Document Title: CYP15G0401TB Quad HOTLink II™ Transmitter Document Number: 38-02112 ECN Issue Orig. of REV. No. Date Change ** 318023 See ECN REV Document #: 38-02112 Rev. ** PRELIMINARY Description of Change New Data Sheet CYP15G0401TB Page [+] Feedback ...