ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 34

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 5
3.2.2
Figure 6
sense is detected, which causes CRSDV to assert asynchronously to REFCLK. The received data is then placed
into the FIFO for resynchronization. After a minimum of 12 bits are placed into the FIFO, the received data is
presented onto RXD[1:0] synchronously to REFCLK. Note that while the FIFO is filling up RXD[1:0] is set to 00
until the first received di-bit of preamble (01) is presented onto RXD[1:0]. When carrier sense is de-asserted at the
end of a packet, CRSDV is de-asserted when the first di-bit of a nibble is presented onto RXD[1:0] synchronously
to REFCLK. If there is still data in the FIFO that has not yet been presented onto RXD[1:0], then on the second di-
bit of a nibble, CRSDV reasserts. This pattern of assertion and de-assertion continues until all received data in the
FIFO has been presented onto RXD[1:0]. RXER is inactive for the duration of the received valid packet.
Figure 7
CRSDV is asserted asynchronously to REFCLK as in the valid receive case shown in . However, once false carrier
is detected, RXD[1:0] is changed to (10) (11) (Value 1110 in MII) and RXER is asserted. Both RXD[1:0] and RXER
transition synchronously to REFCLK. After carrier sense is de-asserted, CRSDV is de-asserted synchronously to
REFCLK.
Figure 6
Data Sheet
shows the relationship among REFCLK, CRSDV, RXD and RXER while receiving a valid packet. Carrier
shows the relationship among REFCLK, CRSDV and RXD[1:0] during a received false carrier event.
RMII Signal Diagram
Receive Path for 100M
RMII Reception Without Error
34
Function Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001