ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 47

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ADM7001XACT1XP

Manufacturer Part Number
ADM7001XACT1XP
Description
Manufacturer
Lantiq
Datasheet

Specifications of ADM7001XACT1XP

Lead Free Status / RoHS Status
Supplier Unconfirmed
4
Table 18
Module
PHY
Table 19
Register Short Name
CR
SR
PHY_IR0
PHY_IR1
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ANLPA
ANER
Res0
GPCR
P10_MCR
P100_MCR
LCR
IER
PGSR
PSSR
PRVSR
ISR
RECR
CIR
The register is addressed wordwise.
Table 20
Mode
read/write
read
write
read/write
hardware
affected
Data Sheet
Registers Description
Registers Address Space
Registers Overview
Registers Access Types
Symbol Description Hardware (HW)
rw
r
w
rwh
rwv
Base Address
00
Register Long Name
Control Register
Status Register
PHY Identifier Register 0
PHY Identifier Register 1
Auto Negotiation Advertisement Register
Auto Negotiation Link Partner Ability
Auto Negotiation Expansion Register
Reserved 0
Generic PHY Control/Configuration Register
PHY 10M Module Configuration Register
PHY 100M Module Control Register
LED Configuration Register
Interrupt Enable Register
PHY Generic Status Register
PHY Specific Status Register
PHY Recommend Value Status Register
Interrupt Status Register
Receive Error Counter Register
Chip ID Register
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register can be modified by HW
H
End Address
1F
H
47
Description Software (SW)
Register is read and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
Register is writable by SW
Register can be modified by HW, but the
priority SW versus HW has to be specified
Note
Offset Address
00
01
02
03
04
05
06
07
10
11
12
13
14
16
17
18
19
1D
1F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Registers Description
Rev. 1.07, 2005-09-12
Page Number
49
51
54
54
55
56
57
58
59
61
63
64
66
67
68
69
70
71
72
Data sheet
ADM7001

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