FWLXT9785EBC.D0 Cortina Systems Inc, FWLXT9785EBC.D0 Datasheet - Page 119

• Manufacturer Part Number: FWLXT9785EBC.D0
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785EBC.D0

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.3.7
Note:
Figure 9
Figure 10
Cortina Systems
MDIO Management Interface
The LXT9785/LXT9785E supports the IEEE 802.3 MII Management Interface, also known
as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer
devices to monitor and control the state of the LXT9785/LXT9785E. The MDIO interface
consists of a physical connection, a specific protocol that runs across the connection, and
an internal set of addressable registers. Some registers are required and their functions
are defined by the IEEE 802.3 specification. Additional registers allow for expanded
functionality. Specific bits in the registers are referenced using an “X.Y” notation, where X
is the register number (0-32) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of
this interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs
are completely disabled. The Hardware Control Interface provides primary configuration
control. When MDDIS is Low, the MDIO port is enabled for both read and write operations
and the Hardware Control Interface is not used.
The BGA15 package does not support the MDDIS pin.
The timing for the MDIO Interface is shown in
page
Read Frame Structure, on page 119
Structure, on page
Management Interface Read Frame Structure
Management Interface Write Frame Structure
The protocol allows one controller to communicate with multiple LXT9785/LXT9785E
devices. Pins ADD_<4:0> determine the base address. Each port adds its port number to
the base address to obtain its port address as shown in
The BGA15 package uses a similar scheme where the ADD_[2:0] bits internally set to 0
and the ADD_[4:3] bits are used to select from four base addresses (0x00000b,
0x01000b, 0x10000b, or 0x11000b.
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
(Write)
MDIO
(Read)
MDC
MDIO
MDC
High Z
189. MDIO read and write cycles are shown in
Idle
Preamble
32 "1"s
Preamble
32 "1"s
0
0
ST
ST
119.
1
1
1
0
Op Code
Op Code
0
1
Write
A4
A4
PHY Address
PHY Address
A3
A3
and
A0
A0
Figure 10, Management Interface Write Frame
Write
R4
R4
Register Address
Register Address
Table 80, MDIO Timing Parameters, on
R3
R3
R0
R0
Figure 9, Management Interface
Figure
Z
Around
Turn
1
Around
Turn
0
0
D15
11.
D15
D15
D14
Interface (MII) Interfaces
Data
Read
4.3 Media Independent
D14
D14
D1
Data
D1
D1
D0
D0
Idle
Page 119
Idle