FWLXT9785EBC.D0 Cortina Systems Inc, FWLXT9785EBC.D0 Datasheet - Page 124

• Manufacturer Part Number: FWLXT9785EBC.D0
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9785EBC.D0

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 13
4.5.3
Note:
Note:
Cortina Systems
Initialization Sequence
Power-Down Mode
The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power
possible. The device can be put into a low-power state via Register 0 as well as a near-
zero power state with the power down pin. When in power-down mode, the device is not
capable of receiving or transmitting packets.
The lowest power operation is achieved using the Global power-down pin, which is active
High. This pin powers down every circuit in the device, including all clocks. All registers
are unaltered and maintained when the Global PWRDWN pin is released.
The BGA15 package does not support the PWRDWN pin feature.
Individual ports (software power down) can be powered down using Register bit 0.11. This
bit powers down a significant portion of the port, but clocks to the register section remain
active. This allows the management interface to remain active during register power-
down. The power-down bit is active High.
Cortina recommends that a minimum recovery time be allowed after bringing up a port
from software or hardware power-down or link hold-off modes. The recovery times are
specified in
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 81, Power-Up Timing Parameters, on page 190
Reset MDIO Registers to
Control Interface at last
Pass Control to MDIO
MDIO Control
values read at H/W
Hardware Reset
Mode
Software
Interface
Reset?
Yes
Low
Initialize MDIO Registers
Power-up or Reset
Read H/W Control
MDDIS Voltage
Interface
Level?
Disable MDIO Writes
High
Hardware Control
Hardware
Reset?
Mode
Yes
4.5 Initialization
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