CY7B9334-270JC Cypress Semiconductor Corp, CY7B9334-270JC Datasheet - Page 19

• Manufacturer Part Number: CY7B9334-270JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B9334-270JC

• Lead Free Status / RoHS Status: Not Compliant

BIST Mode
BIST mode functions as follows:
Document #: 38-02014 Rev. *B
1. Set BISTEN LOW to begin test pattern generation. Trans-
2. Set either ENA or ENN LOW to begin pattern sequence
mitter begins sending bit rate ...1010...
generation (use of the Enable pin not being used for normal
FIFO or system interface can minimize logic delays between
the controller and transmitter).
START
Tx
BEGIN
TEST
Rx
ERROR
START
TEST
LOOP
BIST
LOOP
BIST
Figure 7. Built In Self-Test Illustration
TEST
END
STOP
WITHIN SPEC.
WITHIN SPEC.
Tx
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
HIGH
LOW
LOW
8
8
Note: It may be advisable to send violation characters to test the
RVS output in the Receiver. This can be done by explicitly
sending a violation with the SVS input, or allowing the transmitter
BIST loop to run while the Receiver runs in normal mode. The
3. Allow the Transmitter to run through several BIST loops or
4. When testing is completed, set BISTEN HIGH and ENA and
until the Receiver test is complete. RP will pulse LOW once
per BIST loop, and can be used by an external counter to
monitor the number of test pattern loops.
ENN HIGH and resume normal function.
FOTO
MODE
CKW
RP
SC/D
D
SVS
ENA
ENN
BISTEN
REFCLK
MODE
RF
CKR
SC/D
Q
RVS
RDY
BISTEN
0 − 7
0 − 7
CY7B9234
CY7B9334
OUTC
OUTA
OUTB
INA
INB
A/B
SO
DON'T CARE
LOW
CY7B9234
CY7B9334
Page 19 of 36
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