L80223 LSI, L80223 Datasheet - Page 50
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L80223
Manufacturer Part Number
L80223
Description
Manufacturer
LSI
Datasheet
1.L80223.pdf
(140 pages)
Specifications of L80223
Lead Free Status / RoHS Status
Not Compliant
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2.5.1 100 Mbits/s
2.5.2 10 Mbits/s
2-32
The End of Stream Delimiter (ESD) indicates the end of packet for 100
Mbits/s mode. The ESD pattern consists of two /T/R/ 4B5B symbols
inserted after the end of the packet, as defined in IEEE 802.3 Clause 24
and shown in
The 4B5B encoder generates the transmit ESD and inserts the /T/R/
symbols after the end of the transmit data packet, as shown in
Figure
The 4B5B decoder detects the ESD pattern when there are groups of 10
consecutive code bits (two 5B words) from the descrambler during valid
packet reception.
If the 10 consecutive code bits from the receiver during valid packet
reception consist of the /T/R/ symbols, the end of packet is detected,
data reception is terminated, the CRS and RX_DV pins are asserted, and
/I/I/ symbols are substituted in place of the /T/R/ symbols.
If the 10 consecutive code bits from the receiver during valid packet
reception do not consist of /T/R/ symbols, but instead consist of /I/I/
symbols, the packet is considered to have been terminated prematurely
and abnormally, and the end of packet condition is signalled to the
controller interface.
When the premature end of packet condition is detected, the RX_ER
signal is asserted for the nibble associated with the first /I/ symbol
detected, then the CRS and RX_DV pins are deasserted.
The end of packet for 10 Mbits/s mode is indicated with the Start of Idle
(SOI) pulse. The SOI pulse is a positive double wide pulse containing a
Manchester code violation inserted at the end of every packet.
The TP transmitter generates the transmit SOI pulse and inserts it at the
end of the data packet after TX_EN has been deasserted. The transmit
waveshaper shapes the transmitted SOI output pulse at the TP output to
meet the pulse template requirements specified in IEEE 802.3 Clause 14
and shown in
Functional Description
2.2.
Table 2.4
Figure
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
2.8.
and
Figure
2.2.