HBLXT9785HE.D0 Intel, HBLXT9785HE.D0 Datasheet - Page 81

• Manufacturer Part Number: HBLXT9785HE.D0
• Manufacturer: Intel

Specifications of HBLXT9785HE.D0

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 24
Cortina Systems
RMII Signal Descriptions – BGA23 (Sheet 2 of 3)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
BGA23
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
A13,
B14,
C15,
C12
B15
B17
C2,
D9,
A3,
B6,
C7
Designation
B1
B4
B9
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
Power-Down modes and during H/W reset.
Ball/Pin
PQFP
206
205
55
54
46
45
37
36
28
27
16
15
8
7
RxData0_0
RxData0_1
RxData1_0
RxData1_1
RxData2_0
RxData2_1
RxData3_0
RxData3_1
RxData4_0
RxData4_1
RxData5_0
RxData5_1
RxData6_0
RxData6_1
Symbol
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
O, TS, ID
Type
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
1
Signal Description
Receive Data - Port 0.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 1.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 2.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 3.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 4.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 5.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
Receive Data - Port 6.
Receive data signals (2-bit parallel di-bits) are driven
synchronously to REFCLK.
3.4 BGA23 Signal Descriptions
2,3
Page 81