EGLXT973QEA3V Intel, EGLXT973QEA3V Datasheet
EGLXT973QEA3V
Specifications of EGLXT973QEA3V
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EGLXT973QEA3V Summary of contents
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... Cortina Systems Dual-Port Fast Ethernet PHY Transceiver Specification Update 20 March 2007 Document Number 249737 Revision 10.0 This document contains information proprietary to Cortina Systems, Inc. Any use or disclosure, in whole or in part, of this information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as authorized by Cortina Systems, Inc ...
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... Status....................................................................................................................... 6 3.2 Errata .................................................................................................................................... 6 3.3 Specification Changes .......................................................................................................... 7 3.4 Specification Clarifications.................................................................................................... 7 3.5 Documentation Changes ...................................................................................................... 7 4.0 Identification Information .............................................................................................................8 4.1 Markings ............................................................................................................................... 8 5.0 Errata ............................................................................................................................................ 10 6.0 Specification Changes ................................................................................................................ 15 7.0 Specification Clarifications......................................................................................................... 16 8.0 Documentation Changes ............................................................................................................ 17 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Contents Page 2 ...
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... V Fiber Speed Selection”. Modified Table 1, “Product Information”. Replaced MM numbers. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision 10.0 Revision Date: 20 March 2007 Revision: 009 Revision Date: 29 November 2005 Information. and Figure 4, Ordering Information – Sample ...
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... Corrected Manufacturer’s Revision Number in Markings table. Added Product Ordering Information. Added Erratum #2. Added Erratum #1. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision: 003 Revision Date: 01 August 2001 Revision: 002 Revision Date: 31 May 2001 Revision: 001 Revision Date: 18 May 2001 1 ...
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... Errata are design defects or errors. These may cause the behavior of the Cortina ® Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver (LXT973 PHY Transceiver) to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the LXT973 PHY Transceiver. Cortina Systems, Inc. component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: 3 ...
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... Revision 1 002 2 003 3 003 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page Status page 12 NoFix Section 8, Changing Advertised Duplex While Link Is Up page 12 NoFix Section 9, Detection of Illegal Symbols After SSD Section 10, Port 1 LED Functionality Incorrect when Port 0 in ...
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... Figure 1 Example of Top Marking Information Labeled as Cortina Systems, Inc. AAAOOOAAA AywwX00a Country of Origin Figure 2 Sample PQFP Package – Intel* LXT973QC Transceiver Figure 3 shows a sample Pb-free RoHS-compliant PQFP package for the LXT973 PHY Transceiver. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver ...
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... Specification Update 249737, Revision 10.0 20 March 2007 Figure 3 Sample Pb-Free (RoHS-Compliant) PQFP Package – Intel* EGLX973QC Transceiver The silicon stepping in the LXT973 PHY Transceiver Datasheet is referred to as “Manufacturer’s Revision Number”. The silicon stepping revision number may be read by software from Register 3, bits 3:0 in the LXT973 PHY Transceiver. ...
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... Problem Link may not come up reliably when the following occurs: • The LXT973 PHY Transceiver is in forced 100 Mbps mode and link is down. • The link partner is configured to auto-negotiate. • The link partner cannot handle instantaneous jitter on the MLT3 signal during link-up. ...
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... Problem If a link partner continuously sends successive Far-End Fault (FEF) codes (three sets followed by a 0), the LXT973 PHY Transceiver sets the Remote Fault bit High (Register bit 1 and drops link (Register bit 1.2 = 0). Register bit 1.4 is cleared after a Read and is not set High again while the Far-End Fault signal is present. ...
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... Writing to Register bits 4.9:5, which control duplex mode advertisement while link is up and auto-negotiation is enabled, immediately changes the PHY mode of operation to the new duplex mode. When written, the values in this register are not intended to affect PHY operation until a new auto-negotiation cycle is completed. ...
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... Workaround Port 0 LEDs function properly when Port 1 is placed in Hardware Power-Down mode with the PWRDWN1 pin result, depending on design requirements, the following options can be used as workarounds: • Use Port 0 and Hardware Power-Down Port 1. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver LEDn_1 LEDn_2 LEDn_3 Speed Link ...
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... March 2007 • Software Power-Down mode is not affected by this erratum. Use Register Bit 0.11 to Power-Down Port0. For design differences between Software and Hardware Power- Down Modes, see the LXT973 PHY Transceiver datasheet’s Section 3.5.3, “Power- Down Mode”. Note: • For designs that require the MII interface to be isolated, use Register Bit 0.10. ...
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... LXT973 PHY Transceiver Specification Update 249737, Revision 10.0 20 March 2007 6.0 Specification Changes There are no specification changes. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 6.0 Specification Changes Page 15 ...
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... LXT973 PHY Transceiver Specification Update 249737, Revision 10.0 20 March 2007 7.0 Specification Clarifications There are no specification clarifications. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 7.0 Specification Clarifications Page 16 ...
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... LXT973 PHY Transceiver product ordering information. the ordering information matrix. Table 3 Product Ordering Information Number SLXT973QC.A3V EGLXT973QC.A3V SLXT973QE.A3V EGLXT973QE.A3V ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision Package Type Pin Count A3 PQFP 100 A3 PQFP 100 A3 ...
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... T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA (BGA with heat slug Product Code xxxxx = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device (MAC/Framer) IXP = Network processor Intel Package Designator Pb-Free 8.0 Documentation Changes Package Leaded WB ...
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... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-Down ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Type Signal Description OLD Information in table - Management Disable. When MDDIS0 is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power-up and reset ...
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... Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver © Cortina Systems, Inc. 2001−2007 End of Document Contact Information ...