HBLXT9785HC.C2 Intel, HBLXT9785HC.C2 Datasheet - Page 174

• Manufacturer Part Number: HBLXT9785HC.C2
• Manufacturer: Intel

Specifications of HBLXT9785HC.C2

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 60
Figure 39
Cortina Systems
10BASE-T Transceiver Characteristics
SMII - 100BASE-TX Receive Timing
®
Peak differential output voltage
Link transmit period
Jitter magnitude added by the
MAU and PLS sections
Receive input impedance
Link min receive timer
Link max receive timer
Differential squelch threshold
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5
4. After line model specified by IEEE 802.3 for 10BASE-T MAU.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
REFCLK
testing.
ns from the MAU.
RxData
SYNC
TPFI
Parameter
3,4
3
t
3
TLRmax
TLRmin
Sym
V
t
V
Z
tx-jit
OP
–
DS
IN
t
5
t
6
Min
2.2
Transmitter
50
8
–
–
2
–
Receiver
Typ
t
100
475
1
2.5
–
–
–
–
1
Max
150
2.8
24
11
–
7
–
t
2
mV Peak
Units
ms
ms
ms
ns
W
V
6.0 Test Specifications
t
4
Between TPFIP and
5 MHz square wave
Test Conditions
Note 2
TPFIN
input
–
–
–
–
Page 174