KS8721BL A4 TR Micrel Inc, KS8721BL A4 TR Datasheet - Page 6

• Manufacturer Part Number: KS8721BL A4 TR
• Manufacturer: Micrel Inc

Specifications of KS8721BL A4 TR

• Lead Free Status / RoHS Status: Not Compliant

KS8721BL/SL
Pin Description
Notes:
1. P = Power supply.
M9999-022105
Pin Number
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.
10
12
13
14
15
16
17
18
11
1
2
3
4
5
6
7
8
9
PCS_LPBK
RXER/ISO
Pin Name
PHYAD2
PHYAD3
PHYAD4
REFCLK
CRSDV/
PHYAD
VDDIO
RXDV/
RXD3/
RXD2/
RXD1/
RXD0/
VDDC
TXER
TXEN
MDIO
TXD0
TXD1
MDC
TXC/
GND
RXC
GND
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
GND
GND
Ipd
Ipd
Ipd
Ipd
I/O
I/O
O
P
P
I
(1)
Pin Function
Management Independent Interface (MII) Data I/O. This pin requires an external
4.7K pull-up resistor.
MII Clock Input. This pin is synchronous to the MDIO.
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See
“Strapping Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See
“Strapping Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR [3]. See
“Strapping Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See
“Strapping Options” section for details.
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage
regulator. See “Circuit Design Ref. for Power Supply" section for details.
Ground.
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See
“Strapping Options” section for details.
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
Ground.
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply"
section for details.
MII Transmit Error Input.
MII Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for
REF clock interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave
MII Transmit Enable Input.
MII Transmit Data Input.
MII Transmit Data Input.
XO pin unconnected.
6
February 2005
Micrel