EELXT901APC.A4 S L8L5 Cortina Systems Inc, EELXT901APC.A4 S L8L5 Datasheet - Page 12

• Manufacturer Part Number: EELXT901APC.A4 S L8L5
• Manufacturer: Cortina Systems Inc

Specifications of EELXT901APC.A4 S L8L5

• Lead Free Status / RoHS Status: Compliant

LXT901/907 — Universal 10BASE-T and AUI Transceivers
2.1
2.2
12
Table 2.
Figure 3. LXT901/907 TPO Output Waveform
Controller Compatibility Modes
The LXT901/907 ia compatible with most industry standard controllers, including devices
produced by Motorola, AMD, Intel, Fujitsu, National Semiconductor, Seeq, and Texas Instruments.
Four different control signal timing and polarity schemes (Modes 1 through 4) are required to
achieve this compatibility. Mode select pins (MD0 and MD1) determine controller compatibility
modes as listed in
each mode.
Controller Compatibility Modes
Transmit Function
The LXT901/907 receives NRZ data from the controller at the TXD input, as shown in
“LXT901/907 Block Diagram” on page
encoded data is then transferred to either the AUI cable (DO circuit) or the twisted-pair network
(TPO circuit). The advanced integrated pulse shaping and filtering network produces the output
signal on TPON and TPOP, as shown in
to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to
remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters
simplify the design work required for FCC compliant EMI performance. During idle periods, the
LXT901/907 transmits link integrity test pulses on the TPO circuit (if LI is enabled and integrated,
PLS/ MAU mode is selected). External resistors control the termination impedance for the
LXT907. External resistors and the STP pin control termination impedance on the LXT901.
Mode 1
For Motorola 68EN360, MPC860, Advanced Micro Devices AM7990, or compatible
controllers
Mode 2
For Intel 82596 or compatible controllers
Mode 3
For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)
Mode 4
For National Semiconductor 8390 or compatible controllers (TI TMS380C26)
1. Refer to Intel Application Note 51 when designing with Intel controllers.
2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
Table
2. Refer to Test Specifications for a complete set of timing diagrams for
Controller Mode
1
7, and passes it through a Manchester encoder. The
Figure
3. The TPO output is pre-distorted and pre-filtered
2
Rev. Date: June 19, 2001
Document #: 249097
MD1
High
High
Low
Low
Revision #: 002
Setting
Datasheet
Figure 1,
MD0
High
High
Low
Low