EELXT901APC.A4 S L8L5 Cortina Systems Inc, EELXT901APC.A4 S L8L5 Datasheet - Page 17

• Manufacturer Part Number: EELXT901APC.A4 S L8L5
• Manufacturer: Cortina Systems Inc

Specifications of EELXT901APC.A4 S L8L5

• Lead Free Status / RoHS Status: Compliant

2.4.3
2.4.4
2.5
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Forced Twisted-Pair Loopback
“Forced” twisted-pair loopback is controlled by the LBK pin. When the twisted-pair port is
selected and LBK is High, twisted-pair loopback is “forced”, overriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effect.
AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-end is internally looped back from the TXD pin through the
Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs.
Link Integrity Test Function
Figure 7 on page 18
integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity
testing is enabled when the LI pin is tied High. When enabled, the receiver recognizes link integrity
pulses which are transmitted in the absence of receive traffic. If no serial data stream or link
integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the
transmit and normal loopback functions. The LXT901/907 ignores any link integrity pulse with
interval less than 2 - 7 ms. The LXT901/907 will remain in the link fail state until it detects either a
serial data packet or two or more link integrity pulses.
is a state diagram of the LXT901/907 Link Integrity test function. The link
Universal 10BASE-T and AUI Transceivers — LXT901/907
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