SI3206-B-GQ Silicon Laboratories Inc, SI3206-B-GQ Datasheet - Page 78

• Manufacturer Part Number: SI3206-B-GQ
• Description: IC PROSLIC LINE FEED 125V 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3206-B-GQ

• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Longitudinal Balanced: 63
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Loop Current Limit: 45mA
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Function: Subscriber Line Interface Concept (SLIC)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 4
• Voltage - Supply: 3.3V
• Current - Supply: *
• Power (watts): *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad
• Includes: *
• Lead Free Status / RoHS Status: Compliant

Si3232
MSTRSTAT: Master Initialization Status (Register Address 3)
(Register type: Initialization/single value instance for both channels)
Reset settings = 0x00
78
Name PLLFAULT FSFAULT PCFAULT
Type
Bit
Bit
7
6
5
4
3
2
1
0
PLLFAULT
PCFAULT
FSFAULT
SRCLR
PLOCK
FSDET
PCVAL
FSVAL
Name
R/W
D7
PLL Lock Fault Status.
This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to
this bit clears the status.
0 = PLL lock is valid.
1 = PLL has lost lock.
FSYNC Clock Fault Status.
This bit is set when the FSVAL and FSDET bits transition low, indicating loss of valid
FSYNC signal or invalid FSYNC-to-PCLK ratio. Writing 1 to this bit clears the status.
0 = Correct FSYNC to PCLK ration present.
1 = FSYNC to PCLK ratio lost.
PCM Clock Fault Status.
This bit will be set when the PCVAL bit transitions low. Writing 1 to this bit clears the status.
0 = Valid PCLK signal present.
1 = No valid PCLK signal present.
SRAM Clear Status Detect.
0 = SRAM clear operation not initiated or in progress.
1 = SRAM clear operation has completed.
PLL Lock Detect.
Indicates the internal PLL is locked relative to FSYNC.
0 = PLL has lost lock relative to FSYNC.
1 = PLL locked relative to FSYNC.
FSYNC to PCLK Ratio Detect.
Indicates a valid FSYNC to PCLK ratio has been detected.
0 = Invalid FSYNC to PCLK ratio detected.
1 = Correct FSYNC to PCLK ratio present.
FSYNC Clock Valid.
Indicates that a minimum valid FSYNC signal is present.
0 = FSYNC signal is not valid.
1 = FSYNC signal is present.
PCM Clock Valid.
Indicates that a minimum valid PCLK signal is present.
0 = PCLK signal is ≤ 128 kHz.
1 = PCLK signal is ≥ 128 kHz.
R/W
D6
R/W
D5
SRCLR
Preliminary Rev. 0.96
D4
R
PLOCK
D3
R
Function
FSDET
D2
R
FSVAL
D1
R
PCVAL
D0
R