DS92LX2121SQE National Semiconductor, DS92LX2121SQE Datasheet - Page 13

• Manufacturer Part Number: DS92LX2121SQE
• Description: SERDES, 10-50MHZ, 40LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2121SQE

• Data Rate: 1.05Gbps
• No. Of Inputs: 21
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 40
• Base Number: 2121
• Operating Temperature Range: -40°C To +85°C
• Serdes Function: Serializer
• Ic Input Type: LVCMOS
• Ic Output Type: LVCMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

V
V
V
I
I
C
V
OZ
IN
IH
IL
HY
OL
IN
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device
should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, T
characterization and are not guaranteed.
Note 5: t
Note 6: t
Note 7: t
Note 8: t
Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to the V
supply with amplitude = 25 mVp-p measured at the device V
no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.
Note 10: Specification is guaranteed by design and is not tested in production.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: Recommended Input Timing Requirements are input specifications and not tested in production.
Note 13: UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Note 14: t
Symbol
PLD
DCJ
DPJ
DCCJ
RJIT
is the maximum amount the period is allowed to deviate measured over 30,000 samples.
and t
is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
max (0.61UI) is limited by instrumentation and actual t
DDLT
Input High Level
Input Low Level Voltage
Input Hysteresis
TRI-STATE® Output
Current
Input Current
Input Pin Capacitance
Low Level Output Voltage
is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
Parameter
SDA and SCL
SDA and SCL
PDB = 0V VOUT = 0V or VDD
SDA or SCL, Vin = V
SCL and SDA VDDIO = 3.0V IOL = 1.5
mA
SCL and SDA VDDIO = 1.71V IOL = 1
mA
FIGURE 3. Serial Control Bus Timing
DDn
pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows
RJIT
Conditions
of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
13
A
DDIO
= +25°C, and at the Recommended Operation Conditions at the time of product
or GND
V
0.7 x
GND
Min
-20
-20
DDIO
Typ
>50
±1
±1
<5
2
C Compliant
V
V
0.3 x
Max
0.36
0.36
+20
+20
DDIO
DDIO
30125136
www.national.com
DDn
Units
mV
(1.8V)
µA
µA
pF
V
V
V
V