DS92LX2121SQE National Semiconductor, DS92LX2121SQE Datasheet - Page 6

• Manufacturer Part Number: DS92LX2121SQE
• Description: SERDES, 10-50MHZ, 40LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2121SQE

• Data Rate: 1.05Gbps
• No. Of Inputs: 21
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 40
• Base Number: 2121
• Operating Temperature Range: -40°C To +85°C
• Serdes Function: Serializer
• Ic Input Type: LVCMOS
• Ic Output Type: LVCMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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LVCMOS PARALLEL INTERFACE
ROUT[20:0]
PCLK
General Purpose Input (GPI)
GPI[3:0]
SERIAL CONTROL BUS - I
SCL
SDA
M/S
CAD
CONTROL AND CONFIGURATION
PDB
LOCK
RES
BIST MODE
BISTEN
PASS
Channel Link III INTERFACE
DS92LX2122 Deserializer Pin Descriptions
Pin Name
5, 6, 8, 9, 10, 11,
12, 13, 14, 15,
16, 18, 19, 21,
22, 23, 24, 25,
30, 31, 32, 33
38, 39, 43, 46
26, 27, 28
Pin No.
47
48
35
34
44
37
4
2
1
2
C COMPATIBLE
Input, LVCMOS w/
pull up
Input/Output, Digital
Input/Output, Open
Input/Output, Open
Outputs, LVCMOS
Input, LVCMOS w/
Input, LVCMOS w/
Output, LVCMOS
Output, LVCMOS
Output, LVCOMS
Input, analog
I/O, Type
pull down
pull down
Drain
Drain
-
Parallel data outputs.
Pixel Clock Output Pin.
Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by
the OSS_SEL.
General-purpose pins individually configured as inputs; which are used to
control and respond to various commands.
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to V
Data line for serial control bus communication
SDA requires an external pull-up resistor to V
I
M/S = L, Master; device generates and drives the SCL clock line. Device is
connected to slave peripheral on teh bus.
M/S = H, Slave (default); device accepts SCL clock input and is attached to
an I
clock, but uses the clock generated by teh Master for teh data transfer.
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection)
Power down Mode Input Pin.
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in
the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is
shutdown and IDD is minimized.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
Reserved.
Pin 43: Leave pin open.
Pin 46: This pin MUST be tied LOW.
Pins 38, 39: Route to test point as differential pair or leave open if unused.
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
2
C Mode Select
2
C controller master on the bus. Slave mode does not generate the SCL
6
Description
DDIO
DDIO
.
.