DS92LX2121SQE National Semiconductor, DS92LX2121SQE Datasheet - Page 25

• Manufacturer Part Number: DS92LX2121SQE
• Description: SERDES, 10-50MHZ, 40LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2121SQE

• Data Rate: 1.05Gbps
• No. Of Inputs: 21
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 40
• Base Number: 2121
• Operating Temperature Range: -40°C To +85°C
• Serdes Function: Serializer
• Ic Input Type: LVCMOS
• Ic Output Type: LVCMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
The DS92LX2121 / DS92LX2122 Channel Link III chipset is
intended for camera applications. The Serializer/ Deserializer
chipset operates from a 10 MHz to 50 MHz pixel clock fre-
quency. The DS92LX2121 transforms a 21-bit wide parallel
LVCMOS data bus along with a bi-directional back channel
control bus into a single high-speed differential pair. The high
speed serial bit stream contains an embedded clock and DC-
balance information which enhances signal quality to support
AC coupling. The DS92LX2122 receives the single serial data
stream and converts it back into a 21-bit wide parallel data
bus together with the back channel data bus.
The control channel function of the DS92LX2121 /
DS92LX2122 provides bi-directional communication between
the image sensor and Electronic Control Unit (ECU). The in-
tegrated back channel transfers data bi-directionally over the
same differential pair used for video data interface. This in-
terface offers advantages over other chipsets by eliminating
the need for additional wires for programming and control.
The back channel bus is controlled via an I
directional back channel offers asymmetrical communication
and is not dependent on video blanking intervals.
The High Speed Forward Channel is a 28-bit symbol com-
posed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1
and CLK0 represent the embedded clock in the serial stream.
CLK1 is always HIGH and CLK0 is always LOW. This data
payload is optimized for signal transmission over an AC cou-
pled link. Data is randomized, balanced and scrambled.
The bi-directional control channel data is transferred along
with the high-speed forward data over the same serial link.
This architecture provides a full duplex low speed forward
channel across the serial link together with a high speed for-
ward channel without the dependence of the video blanking
phase.
DESCRIPTION OF BI-DIRECTIONAL CONTROL BUS AND
I
The I
DS92LX2121, DS92LX2122, or an external remote device
(such as a display) through the bi-directional control channel.
Register
DS92LX2121 / DS92LX2122 chipset are employed through
the clock (SCL) and data (SDA) lines. These two signals have
open drain I/Os and both lines must be pulled-up to V
external resistor.
the clock (SCL) and data (SDA) signals. Pull-up resistors or
2
C MODES
2
C compatible interface allows programming of the
programming
Figure 3
shows the timing relationships of
transactions
FIGURE 19. Serial Bitstream for 28-bit Symbol
2
C port. The bi-
to/from
DDIO
the
by
25
DISPLAY APPLICATION
The DS92LX2121 / DS92LX2122 chipset is intended for in-
terface between a host (graphics processor, FPGA, etc.) and
a Display. It supports a 21 bit parallel video bus for 18-bit color
depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R [5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and
three control bits (VS, HS and DE) are supported across the
serial link. The DS92LX2121 Serializer accepts a 21-bit par-
allel data bus along with a bi-directional control bus. The
parallel data and bi-directional control channel information is
converted into a single differential link. The integrated bi-di-
rectional control channel bus supports I
ation for controlling auxiliary data transport to and from host
processor and display module. The DS92LX2122 Deserializ-
er extracts the clock/control information from the incoming
data stream and reconstructs the 21-bit data with control
channel data.
SERIAL FRAME FORMAT
The DS92LX2121 / DS92LX2122 chipset will transmit and
receive a pixel of data in the following format:
current sources are required on the SCL and SDA busses to
pull them high when they are not being driven low. A logic zero
is transmitted by driving the output low. A logic high is trans-
mitted by releasing the output and allowing it to be pulled-up
externally. The appropriate pull-up resistor values will depend
upon the total bus capacitance and operating speed. The
DS92LX2121 / DS92LX2122 I
100 kbps according to I2C specification.
To start any data transfer, the DS92LX2121 / DS92LX2122
must be configured in the proper I2C mode. Each device can
function as an I
the mode determined by M/S pin. The Ser/Des interface acts
as a virtual bridge between the host device and the remote
device. When the M/S pin is set to HIGH, the device is treated
as a slave proxy; and acts as a slave on behalf of the remote
slave. When addressing a remote peripheral or Serializer/
Deserializer (not wired directly to the host device), the slave
proxy will forward any byte transactions sent by the host con-
troller to the target device. When M/S pin is set to LOW, the
device will function as a master proxy device, and acts as a
master on behalf of the I
devices must have complementary settings for the M/S con-
figuration. For example, if the Serializer M/S pin is set to HIGH
then the Deserializer M/S pin must be set to LOW and vice-
versa.
2
C slave proxy or master proxy depending on
2
C master controller. Note that the
2
C bus data rate supports up to
2
C compatible oper-
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