PIC16F1507-E/SO Microchip Technology, PIC16F1507-E/SO Datasheet - Page 167

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE

PIC16F1507-E/SO

Manufacturer Part Number
PIC16F1507-E/SO
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-E/SO

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOIC-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
PIC16(L)F1507
20.6
REGISTER 20-1:
DS41586A-page 167
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-0/0
LCxEN
CLCx Control Registers
LCxEN: Configurable Logic Cell Enable bit
1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
LCxOE: Configurable Logic Cell Output Enable bit
1 = Configurable logic cell port pin output enabled
0 = Configurable logic cell port pin output disabled
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = LCxIF will be set when a rising edge occurs on lcx_out
0 = LCxIF will not be set
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = LCxIF will be set when a falling edge occurs on lcx_out
0 = LCxIF will not be set
LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K Flip-Flop with R
101 = Cell is 2-input D Flip-Flop with R
100 = Cell is 1-input D Flip-Flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR
R/W-0/0
LCxOE
CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
LCxOUT
R-0/0
LCxINTP
R/W-0/0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
LCxINTN
R/W-0/0
R/W-0/0
LCxMODE<2:0>
 2011 Microchip Technology Inc.
R/W-0/0
R/W-0/0
bit 0

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