PIC16F1507-E/SS Microchip Technology, PIC16F1507-E/SS Datasheet - Page 54

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SSOP .209in TUBE

PIC16F1507-E/SS

Manufacturer Part Number
PIC16F1507-E/SS
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-E/SS

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SSOP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
6.1
The POR circuit holds the device in Reset until V
reached an acceptable level for minimum operation.
Slow rising V
performance may require greater than minimum V
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
6.1.1
The Power-up Timer provides a nominal 64 ms time-
out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the V
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1:
6.2.1
When the BOREN bits of Configuration Words are pro-
grammed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and V
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2
When the BOREN bits of Configuration Words are pro-
grammed to ‘10’, the BOR is on, except in Sleep. The
device start-up will be delayed until the BOR is ready
and V
 2011 Microchip Technology Inc.
BOREN<1:0>
Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR
DD
11
10
01
00
Power-on Reset (POR)
is higher than the BOR threshold.
POWER-UP TIMER (PWRT)
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
BOR IS ALWAYS ON
BOR IS OFF IN SLEEP
DD
, fast operating speeds or analog
BOR OPERATING MODES
SBOREN
X
X
1
0
X
Device Mode
Awake
Sleep
X
X
X
X
DD
DD
has
Preliminary
DD
DD
to
.
BOR Mode
Disabled
Disabled
Disabled
Active
Active
Active
6.2
The BOR circuit holds the device in Reset when V
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A V
gering on small events. If V
duration greater than parameter T
will reset. See
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
6.2.3
When the BOREN bits of Configuration Words are pro-
grammed to ‘01’, the BOR is controlled by the SBO-
REN bit of the BORCON register. The device start-up
is not delayed by the BOR ready condition or the V
level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
DD
noise rejection filter prevents the BOR from trig-
Table 6-1
Brown-Out Reset (BOR)
Release of POR or Wake-up from Sleep
BOR CONTROLLED BY SOFTWARE
Figure 6-2
PIC16(L)F1507
Instruction Exection upon:
for more information.
Waits for BOR ready
Waits for BOR ready
Waits for BOR ready
Begins immediately
(BORRDY = 1)
(BORRDY = 1)
(BORRDY = 1)
(BORRDY = x)
for more information.
DD
falls below V
BORDC
DS41586A-page 54
(1)
(1)
, the device
BOR
for a
DD
DD

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