PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 162
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F1847-I/SO
Manufacturer Part Number
PIC16F1847-I/SO
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
Manufacturer
Microchip Technology
Datasheets
1.PIC16F1847-ISO.pdf
(408 pages)
2.PIC16F1847-ISO.pdf
(408 pages)
3.PIC16F1847-ISO.pdf
(10 pages)
Specifications of PIC16F1847-I/SO
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1847-I/SO
Manufacturer:
MICROCHIP
Quantity:
30 000
- Current page: 162 of 408
- Download datasheet (4Mb)
PIC16(L)F1847
REGISTER 18-2:
DS41453B-page 162
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
SRSPE
SRSPE: SR Latch Peripheral Set Enable bit
1 = SR latch is set when the SRI pin is high
0 = SRI pin has no effect on the set input of the SR latch
SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = SRCLK has no effect on the set input of the SR latch
SRSC2E: SR Latch C2 Set Enable bit
1 = SR latch is set when the C2 Comparator output is high
0 = C2 Comparator output has no effect on the set input of the SR latch
SRSC1E: SR Latch C1 Set Enable bit
1 = SR latch is set when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the set input of the SR latch
SRRPE: SR Latch Peripheral Reset Enable bit
1 = SR latch is reset when the SRI pin is high
0 = SRI pin has no effect on the Reset input of the SR latch
SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with SRCLK
0 = SRCLK has no effect on the Reset input of the SR latch
SRRC2E: SR Latch C2 Reset Enable bit
1 = SR latch is reset when the C2 Comparator output is high
0 = C2 Comparator output has no effect on the Reset input of the SR latch
SRRC1E: SR Latch C1 Reset Enable bit
1 = SR latch is reset when the C1 Comparator output is high
0 = C1 Comparator output has no effect on the Reset input of the SR latch
SRSCKE
R/W-0/0
SRCON1: SR LATCH CONTROL 1 REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
SRSC2E
R/W-0/0
SRSC1E
R/W-0/0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
SRRPE
SRRCKE
R/W-0/0
2011 Microchip Technology Inc.
SRRC2E
R/W-0/0
SRRC1E
R/W-0/0
bit 0
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