PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 30

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1847
TABLE 3-8:
DS41453B-page 30
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
Legend:
Note
Address
Bank 1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB
—
—
—
PIE1
PIE2
PIE3
PIE4
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
These registers can be addressed from any bank.
Name
Shaded locations are unimplemented, read as ‘0’.
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low
A/D Result Register High
Unimplemented
TMR1GIE
STKOVF
T1OSCR
SPLLEN
WPUEN
TRISA7
TRISB7
OSFIE
ADFM
Bit 7
GIE
—
—
—
—
—
—
—
—
Write Buffer for the upper 7 bits of the Program Counter
STKUNF
INTEDG
TRISA6
TRISB6
PLLR
ADIE
Bit 6
PEIE
C2IE
—
—
—
—
—
—
ADCS<2:0>
TMR0CS
TMR0IE
CCP4IE
TRISA5
TRISB5
OSTS
RCIE
Bit 5
C1IE
—
—
—
—
IRCF<3:0>
Preliminary
CHS<4:0>
TMR0SE
CCP3IE
HFIOFR
TRISA4
TRISB4
BSR4
INTE
TXIE
EEIE
Bit 4
TO
—
—
WDTPS<4:0>
TMR6IE
TRISA3
TRISB3
SSP1IE
BCL1IE
RMCLR
HFIOFL
BSR3
IOCE
Bit 3
PSA
PD
—
—
TUN<5:0>
ADNREF
MFIOFR
TMR0IF
CCP1IE
TRISA2
TRISB2
BSR2
Bit 2
PS2
—
—
—
RI
—
Z
GO/DONE
TMR2IE
LFIOFR
TRISA1
TRISB1
TMR4IE
BCL2IE
 2011 Microchip Technology Inc.
BSR1
SCS1
INTF
Bit 1
POR
PS1
DC
—
ADPREF<1:0>
SWDTEN --01 0110 --01 0110
TMR1IE
CCP2IE
HFIOFS
TRISA0
TRISB0
SSP2IE
ADON
BSR0
SCS0
IOCF
Bit 0
BOR
PS0
—
C
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0000 0--0 0000 0--0
--00 0-0- --00 0-0-
---- --00 ---- --00
1111 1111 1111 1111
00-- 11qq qq-- qquu
--00 0000 --00 0000
0011 1-00 0011 1-00
10q0 0q00 qqqq qq0q
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
-000 0000 -000 0000
0000 -000 0000 -000
POR, BOR
Value on
—
—
—
—
Value on
all other
Resets
—
—
—
—