PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 314

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1847
26.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
DS41453A-page 316
APFCON0
APFCON1
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISB
TXSTA
Legend:
never Idle
Name
Reception”), with the following exceptions:
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
Page provides register information.
EUSART Synchronous Slave
Reception
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
SPEN
CSRC
Bit 7
GIE
RECEPTION
—
(Section 26.4.1.5 “Synchronous
SDO1SEL
TRISB6
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
—
SS1SEL
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART Receive Data Register
P2BSEL
TRISB4
Preliminary
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
—
CCP2SEL
SSP1IE
ADDEN
TRISB3
SSP1IF
SENDB
BRG16
IOCE
Bit 3
26.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
P1DSEL
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
Bit 2
—
—
Synchronous Slave Reception
Set-up:
P1CSEL
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
Bit 1
INTF
 2011 Microchip Technology Inc.
—
CCP1SEL
TXCKSEL
TMR1IE
TMR1IF
TRISB0
ABDEN
RX9D
TX9D
IOCF
Bit 0
Register
on Page
294*
120
120
300
299
127
298
89
90
94