PIC16LF1906-E/SS Microchip Technology, PIC16LF1906-E/SS Datasheet - Page 27

• Manufacturer Part Number: PIC16LF1906-E/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-3:
Legend:
00Bh
00Ch
00Dh
00Eh
01Ah
01Bh
01Ch
01Dh
01Eh
000h
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Fh
020h
06Fh
070h
07Fh
Note 1:
Core Registers
(Table
PORTD
BANK 0
T1GCON
96 Bytes
General
Purpose
Register
PORTA
PORTB
PORTC
PORTE
TMR1H
T1CON
TMR1L
TMR0
PIR1
PIR2
PIC16LF1904/7 only.
—
—
—
—
—
—
—
—
= Unimplemented data memory locations, read as ‘0’.
3-2)
(1)
PIC16LF1904/6/7 MEMORY MAP
08Bh
08Ch
08Dh
08Eh
09Ah
09Bh
09Ch
09Dh
09Eh
0A0h
0EFh
0FFh
080h
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Fh
0F0h
Core Registers
OPTION_REG
(Table
OSCSTAT
80 Bytes
WDTCON
70h – 7Fh
BANK 1
OSCCON
Accesses
TRISD
ADRESL
ADRESH
ADCON0
ADCON1
TRISE
General
Purpose
Register
TRISA
TRISB
TRISC
PCON
PIE1
PIE2
—
—
—
—
3-2)
(1)
(1)
(1)
10Bh
10Ch
10Dh
10Eh
11Ah
11Bh
11Ch
11Dh
11Eh
100h
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Fh
120h
13Fh
140h
16Fh
170h
17Fh
Core Registers
80 Bytes
(Table
BORCON
70h – 7Fh
BANK 2
FVRCON
Accesses
LATD
General
Purpose
Register
LATE
LATA
LATB
LATC
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
(1)
(1)
(1)
18Bh
18Ch
18Dh
18Eh
18Fh
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1EFh
1F0h
1FFh
180h
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
Unimplemented
Core Registers
Read as ‘0’
BAUDCON
(Table
70h – 7Fh
BANK 3
PMADRL
PMADRH
PMDATH
PMCON1
PMCON2
SPBRGH
Accesses
ANSELA
ANSELB
PMDATL
RCREG
SPBRG
TXREG
RCSTA
TXSTA
—
—
—
—
—
3-2)
20Bh
20Ch
20Dh
20Eh
20Fh
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
26Fh
27Fh
200h
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
220h
270h
Unimplemented
Core Registers
Read as ‘0’
(Table
70h – 7Fh
BANK 4
Accesses
WPUB
WPUE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
28Bh
28Ch
28Dh
28Eh
28Fh
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
280h
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
Unimplemented
Core Registers
Read as ‘0’
(Table
70h – 7Fh
BANK 5
Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
300h
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h General Purpose
36Fh
370h
37Fh
Unimplemented
Core Registers
Read as ‘0’
(Table
32 Bytes
70h – 7Fh
BANK 6
Accesses
Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
(1)
380h
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
Unimplemented
Core Registers
Read as ‘0’
(Table
70h – 7Fh
BANK 7
Accesses
IOCBN
IOCBP
IOCBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)