PIC16LF1906-E/SS Microchip Technology, PIC16LF1906-E/SS Datasheet - Page 28

• Manufacturer Part Number: PIC16LF1906-E/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-3:
Legend:
40Bh
40Ch
80Bh
80Ch
400h
46Fh
470h
47Fh
800h
86Fh
870h
87Fh
C0Ch
C00h
C0Bh
C6Fh
C70h
C7Fh
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
(Table
70h – 7Fh)
BANK 16
(Table
70h – 7Fh)
(Accesses
(Accesses
BANK 8
BANK 24
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
3-2)
3-2)
3-2)
= Unimplemented data memory locations, read as ‘0’
PIC16LF1904/6/7 MEMORY MAP (CONTINUED)
48Bh
48Ch
4EFh
4FFh
88Bh
88Ch
8EFh
8FFh
480h
4F0h
880h
8F0h
C8Ch
CEFh
C80h
C8Bh
CF0h
CFFh
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 17
Read as ‘0’
(Table
70h – 7Fh)
(Table
70h – 7Fh)
(Accesses
(Accesses
BANK 9
BANK 25
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
3-2)
3-2)
3-2)
50Bh
50Ch
90Bh
90Ch
500h
56Fh
570h
57Fh
900h
96Fh
970h
97Fh
D0Ch
D00h
D0Bh
D6Fh
D70h
D7Fh
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Unimplemented
Core Registers
Common RAM
BANK 10
Read as ‘0’
BANK 18
Read as ‘0’
(Table
70h – 7Fh)
(Table
70h – 7Fh)
(Accesses
(Accesses
BANK 26
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
3-2)
3-2)
3-2)
58Bh
58Ch
5EFh
5F0h
5FFh
98Bh
98Ch
9EFh
9F0h
9FFh
580h
980h
D8Bh
D8Ch
DEFh
DFFh
D80h
DF0h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Unimplemented
Core Registers
Common RAM
BANK 11
Read as ‘0’
70h – 7Fh)
BANK 19
Read as ‘0’
70h – 7Fh)
(Table
(Table
(Accesses
(Accesses
BANK 27
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
3-2)
3-2)
3-2)
A0Ch
60Bh
60Ch
66Fh
67Fh
A00h
A0Bh
A6Fh
A70h
A7Fh
600h
670h
E0Ch
E00h
E0Bh
E6Fh
E70h
E7Fh
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 12
70h – 7Fh)
BANK 20
70h – 7Fh)
(Table
(Accesses
(Table
(Accesses
Read as ‘0’
BANK 28
70h – 7Fh)
(Table
(Accesses
3-2)
3-2)
3-2)
A8Ch
AEFh
AFFh
680h
68Bh
68Ch
6EFh
6F0h
6FFh
A80h
A8Bh
AF0h
E8Ch
EEFh
E80h
E8Bh
EF0h
EFFh
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 13
70h – 7Fh)
BANK 21
70h – 7Fh)
(Table
(Accesses
(Table
(Accesses
Read as ‘0’
BANK 29
70h – 7Fh)
(Table
(Accesses
3-2)
3-2)
3-2)
B0Bh
B0Ch
700h
70Bh
70Ch
76Fh
770h
77Fh
B00h
B6Fh
B70h
B7Fh
F0Ch
F00h
F0Bh
F6Fh
F70h
F7Fh
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 14
(Table
70h – 7Fh)
BANK 22
(Table
70h – 7Fh)
(Accesses
(Accesses
Read as ‘0’
BANK 30
70h – 7Fh)
(Table
(Accesses
3-2)
3-2)
3-2)
B8Bh
B8Ch
BEFh
BFFh
B80h
BF0h
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 23
(Table
70h – 7Fh)
(Accesses
3-2)