PIC16LF1906T-I/SS Microchip Technology, PIC16LF1906T-I/SS Datasheet - Page 158

• Manufacturer Part Number: PIC16LF1906T-I/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906T-I/SS

• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16-bit, 1 x 8-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

PIC16LF1904/6/7
18.1.1.5
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
18.1.1.6
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See
Detection”
FIGURE 18-3:
DS41569A-page 158
Note:
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
(Transmit Shift
BRG Output
(Shift Clock)
TX/CK
TRMT bit
TXIF bit
The TSR register is not mapped in data
memory, so it is not available to the user.
for more information on the Address mode.
TSR Status
Transmitting 9-Bit Characters
pin
ASYNCHRONOUS TRANSMISSION
Word 1
Transmit Shift Reg
Word 1
Section 18.1.2.8 “Address
1 T
CY
Start bit
bit 0
Preliminary
bit 1
Word 1
18.1.1.7
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPBRGH:SPBRGL register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see
Rate Generator
Set the RX/DT and TX/CK TRIS controls to ‘1’.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the 8 Least Significant data bits are an address
when the receiver is set for address detection.
Set the CKTXP control bit if inverted transmit
data polarity is desired.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXREG register. This
will start the transmission.
Asynchronous Transmission Set-up:
bit 7/8
Section 18.3 “EUSART Baud
(BRG)”).
 2011 Microchip Technology Inc.
Stop bit