PIC16LF1906T-I/SS Microchip Technology, PIC16LF1906T-I/SS Datasheet - Page 54
PIC16LF1906T-I/SS
Manufacturer Part Number
PIC16LF1906T-I/SS
Description
14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1904-EMV.pdf
(288 pages)
Specifications of PIC16LF1906T-I/SS
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 16-bit, 1 x 8-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Package / Case
QFN-28
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
LIN, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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PIC16LF1904/6/7
5.11
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset.
conditions of these registers.
TABLE 5-3:
TABLE 5-4:
DS41569A-page 54
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
WDT Wake-up from Sleep
Brown-out Reset
Interrupt Wake-up from Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
STKOVF STKUNF RWDT RMCLR
0
0
0
0
u
u
u
u
u
u
1
u
2: If a Status bit is not implemented, that bit will be read as ‘0’.
Determining the Cause of a Reset
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
Table 5-3
0
0
0
0
u
u
u
u
u
u
u
1
RESET STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
and
1
1
1
u
0
u
u
u
u
u
u
u
Condition
Table 5-4
1
1
1
1
u
u
u
0
0
u
u
u
show the Reset
RI
1
1
1
1
u
u
u
u
u
0
u
u
POR
Preliminary
0
0
0
u
u
u
u
u
u
u
u
u
BOR
x
x
x
0
u
u
u
u
u
u
u
u
Program
PC + 1
Counter
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
TO
1
0
x
1
0
0
1
u
1
u
u
u
(1)
PD
(2)
1
x
0
1
u
0
0
u
0
u
u
u
---1 1000
---u uuuu
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Register
STATUS
2011 Microchip Technology Inc.
Condition
00-1 110x
uu-u 0uuu
uu-u 0uuu
uu-0 uuuu
uu-u uuuu
00-1 11u0
uu-u uuuu
uu-u u0uu
1u-u uuuu
u1-u uuuu
Register
PCON
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