PIC16LF723A-I/MV Microchip Technology, PIC16LF723A-I/MV Datasheet - Page 129
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PIC16LF723A-I/MV
Manufacturer Part Number
PIC16LF723A-I/MV
Description
7 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F722AT-ISS.pdf
(284 pages)
Specifications of PIC16LF723A-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.3
The PWM mode generates a Pulse-Width Modulated
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
• PR2
• T2CON
• CCPRxL
• CCPxCON
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCPx pin.
Figure 15-3 shows a simplified block diagram of PWM
operation.
Figure 15-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, refer to Section 15.3.8
“Setup for PWM Operation”.
FIGURE 15-3:
2010 Microchip Technology Inc.
Note 1:
CCPRxH
Duty Cycle Registers
Comparator
2:
CCPRxL
PWM Mode
PR2
TMR2
Comparator
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (F
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPRxH is a read-only register.
(2)
(Slave)
(1)
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer2,
toggle CCPx pin and
latch duty cycle
CCPxCON<5:4>
S
R
Q
TRIS
OSC
CCPx
), or
PIC16F/LF722A/723A
The PWM output (Figure 15-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 15-4:
15.3.1
In PWM mode, the CCPx pin is multiplexed with the
PORT data latch. The user must configure the CCPx
pin as an output by clearing the associated TRIS bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
Note:
Pulse Width
TMR2 = 0
CCPX PIN CONFIGURATION
Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Period
CCP PWM OUTPUT
TMR2 = CCPRxL:CCPxCON<5:4>
TMR2 = PR2
DS41417A-page 129
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