PIC16LF723A-I/MV Microchip Technology, PIC16LF723A-I/MV Datasheet - Page 166
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PIC16LF723A-I/MV
Manufacturer Part Number
PIC16LF723A-I/MV
Description
7 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F722AT-ISS.pdf
(284 pages)
Specifications of PIC16LF723A-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF722A/723A
17.2.2
During times of no data transfer (Idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through external pull-up resistors. The Start and Stop
conditions determine the start and stop of data trans-
mission. The Start condition is defined as a high-to-low
transition of the SDA line while SCL is high. The Stop
condition is defined as a low-to-high transition of the
SDA line while SCL is high.
FIGURE 17-9:
17.2.3
After the valid reception of an address or data byte, the
hardware automatically will generate the Acknowledge
(ACK) pulse and load the SSPBUF register with the
received value currently in the SSPSR register. There
are certain conditions that will cause the SSP module
not to generate this ACK pulse. They include any or all
of the following:
• The Buffer Full bit, BF of the SSPSTAT register,
• The SSP Overflow bit, SSPOV of the SSPCON
• The SSP module is being operated in Firmware
TABLE 17-2:
DS41417A-page 166
Note 1:
was set before the transfer was received.
register, was set before the transfer was received.
Master mode.
Transfer is Received
Status Bits as Data
BF
0
1
1
0
SDA
SCL
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
START AND STOP CONDITIONS
ACKNOWLEDGE
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
START AND STOP CONDITIONS
Condition
Start
S
SSPSR SSPBUF
Data Allowed
Change of
Yes
No
No
No
Figure 17-9 shows the Start and Stop conditions. A
master device generates these conditions for starting
and terminating data transfer. Due to the definition of
the Start and Stop conditions, when data is being trans-
mitted, the SDA line can only change state when the
SCL line is low.
In such a case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 17-2 shows the results of when a data
transfer byte is received, given the status of bits BF and
SSPOV. Flag bit BF is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
Generate ACK
Pulse
Yes
No
No
No
Data Allowed
Change of
2010 Microchip Technology Inc.
(SSP Interrupt occurs
Condition
Stop
Set bit SSPIF
P
if enabled)
Yes
Yes
Yes
Yes
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