PIC24FJ16GA002-E/SO Microchip Technology, PIC24FJ16GA002-E/SO Datasheet - Page 162
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PIC24FJ16GA002-E/SO
Manufacturer Part Number
PIC24FJ16GA002-E/SO
Description
16-bit Family, 16 MIPS, 16KB Flash, 4096 Bytes RAM, 21 I/O, NanoWatt 28 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ16GA002-E/SO
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- Current page: 162 of 268
- Download datasheet (2Mb)
PIC24FJ64GA004 FAMILY
REGISTER 17-1:
DS39881D-page 162
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
Note 1:
UARTEN
R/C-0, HC
WAKE
R/W-0
2:
3:
(1)
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select” for more information.
This feature is only available for the 16x BRG mode (BRGH = 0).
Bit availability depends on pin availability.
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN1:UEN0: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
LPBACK
R/W-0
minimal
hardware on following rising edge
cleared in hardware upon completion
U-0
—
latches
UxMODE: UARTx MODE REGISTER
®
Encoder and Decoder Enable bit
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R/W-0, HC
ABAUD
USIDL
R/W-0
(1)
IREN
RXINV
R/W-0
R/W-0
(3)
(2)
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
RTSMD
BRGH
R/W-0
R/W-0
PDSEL1
R/W-0
U-0
—
2010 Microchip Technology Inc.
x = Bit is unknown
PDSEL0
R/W-0
R/W-0
UEN1
(3)
R/W-0
STSEL
R/W-0
UEN0
(3)
bit 8
bit 0
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