PIC32MX320F064HT-80I/PT Microchip Technology, PIC32MX320F064HT-80I/PT Datasheet - Page 145

• Manufacturer Part Number: PIC32MX320F064HT-80I/PT
• Description: 64 KB Flash, 16 KB RAM, 40 MHz, 10-Bit ADC 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F064HT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 27-1:
© 2010 Microchip Technology Inc.
JAL
JALR
JALR.HB
JR
JR.HB
LB
LBU
LH
LHU
LL
LUI
LW
LWPC
LWL
LWR
MADD
MADDU
MFC0
MFHI
MFLO
MOVN
MOVZ
MSUB
MSUBU
MTC0
MTHI
MTLO
MUL
MULT
MULTU
NOP
NOR
OR
ORI
RDHWR
Note 1:
Instruction
This instruction is deprecated and should not be used.
MIPS32
Jump and Link
Jump and Link Register
Jump and Link Register with Hazard Barrier
Jump Register
Jump Register with Hazard Barrier
Load Byte
Unsigned Load Byte
Load Halfword
Unsigned Load Halfword
Load Linked Word
Load Upper Immediate
Load Word
Load Word, PC relative
Load Word Left
Load Word Right
Multiply-Add
Multiply-Add Unsigned
Move from Coprocessor 0
Move from HI
Move from LO
Move Conditional on Not Zero
Move Conditional on Zero
Multiply-Subtract
Multiply-Subtract Unsigned
Move to Coprocessor 0
Move to HI
Move to LO
Multiply with register write
Integer Multiply
Unsigned Multiply
No Operation
(Assembler idiom for: SLL r0, r0, r0)
Logical NOR
Logical OR
Logical OR Immediate
Read Hardware Register (if enabled by HWRE
Register)
®
INSTRUCTION SET (CONTINUED)
Description
na
PIC32MX3XX/4XX
GPR[31] = PC + 8
PC = PC[31:28] || offset<<2
Rd = PC + 8
PC = Rs
Like JALR, but also clears execution and
instruction hazards
PC = Rs
Like JR, but also clears execution and
instruction hazards
Rt = (byte)Mem[Rs+offset]
Rt = (ubyte))Mem[Rs+offset]
Rt = (half)Mem[Rs+offset]
Rt = (uhalf)Mem[Rs+offset]
Rt = Mem[Rs+offset>
LL
LLAdr = Rs + offset
Rt = immediate << 16
Rt = Mem[Rs+offset]
Rt = Mem[PC+offset]
Re = Re MERGE Mem[Rs+offset]
Re = Re MERGE Mem[Rs+offset]
HI | LO += (int)Rs * (int)Rt
HI | LO += (uns)Rs * (uns)Rt
Rt = CPR[0, Rd, sel]
Rd = HI
Rd = LO
if Rt ¼ 0 then
if Rt = 0 then
HI | LO -= (int)Rs * (int)Rt
HI | LO -= (uns)Rs * (uns)Rt
CPR[0, n, Sel] = Rt
HI = Rs
LO = Rs
HI | LO =Unpredictable
Rd = ((int)Rs * (int)Rt)
HI | LO = (int)Rs * (int)Rd
HI | LO = (uns)Rs * (uns)Rd
Rd = ~(Rs | Rt)
Rd = Rs | Rt
Rt = Rs | Immed
Re = HWR[Rd]
bit
Rd = Rs
Rd = Rs
= 1
Function
DS61143G-page 145
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