PIC32MX320F064HT-80I/PT Microchip Technology, PIC32MX320F064HT-80I/PT Datasheet - Page 74

• Manufacturer Part Number: PIC32MX320F064HT-80I/PT
• Description: 64 KB Flash, 16 KB RAM, 40 MHz, 10-Bit ADC 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F064HT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-31:
TABLE 4-32:
Legend:
Note
Legend:
Note
6140
6150
6160
6170
6140
6150
6160
6170
1:
1:
PORTF
PORTF
TRISF
ODCF
TRISF
ODCF
LATF
LATF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORT F REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY
PORT F REGISTERS MAP FOR PIC32MX420F032H, PIC32MX440F128H AND PIC2MX440F256H DEVICES ONLY
31/15
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24/8
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
Bits
(1)
23/7
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF6
ODCF6
LATF6
22/6
22/6
RF6
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5
TRISF5
ODCF5
ODCF5
LATF5
LATF5
21/5
21/5
RF5
RF5
—
—
—
—
—
—
—
—
TRISF4
ODCF4
TRISF4
ODCF4
LATF4
LATF4
20/4
20/4
RF4
RF4
—
—
—
—
—
—
—
—
TRISF3
ODCF3
TRISF3
ODCF3
LATF3
LATF3
19/3
RF3
19/3
RF3
—
—
—
—
—
—
—
—
TRISF2
ODCF2
TRISF2
ODCF2
LATF2
LATF2
18/2
18/2
RF2
RF2
—
—
—
—
—
—
—
—
TRISF1
ODCF1
TRISF1
ODCF1
LATF1
LATF1
17/1
17/1
RF1
RF1
—
—
—
—
—
—
—
—
(1)
TRISF0
ODCF0
TRISF0
ODCF0
LATF0
LATF0
16/0
16/0
RF0
RF0
—
—
—
—
—
—
—
—
0000
07FF
0000
xxxx
0000
xxxx
0000
0000
0000
03FF
0000
xxxx
0000
xxxx
0000
0000