PIC32MX320F064HT-80I/PT Microchip Technology, PIC32MX320F064HT-80I/PT Datasheet - Page 166

• Manufacturer Part Number: PIC32MX320F064HT-80I/PT
• Description: 64 KB Flash, 16 KB RAM, 40 MHz, 10-Bit ADC 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F064HT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX3XX/4XX
FIGURE 29-4:
DS61143G-page 166
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Internal Voltage Regulator Enabled
External V
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and S
Note 1: The Power-up period will be extended if the power-up sequence completes before the device
DDCORE
2: Includes interval voltage regulator stabilization delay.
3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled
Power Up Sequence
(Note 2)
Power Up Sequence
(Note 2)
(Note 3)
Power Up Sequence
exits from BOR (V
Provided
POWER-ON RESET TIMING CHARACTERISTICS
V
V
POR
POR
V
POR
DD
(Note 1)
(Note 1)
< V
(T
SY00
(T
SY00
PU
PU
DDMIN
)
)
(T
(T
(Note 1)
SY01
SYSDLY
SY02
PWRT
).
(T
SY10
OSC
)
OST
)
(T
SYSDLY
)
SY02
)
(T
CPU starts fetching code
SYSDLY
SY02
)
)
CPU starts fetching code
V
V
DD
DDCORE
CPU starts fetching code
V
V
DD
DD
© 2010 Microchip Technology Inc.