SST39VF1601C-70-4C-B3KE-T Microchip Technology, SST39VF1601C-70-4C-B3KE-T Datasheet - Page 2

• Manufacturer Part Number: SST39VF1601C-70-4C-B3KE-T
• Description: 2.7V To 3.6V 16Mbit Multi-Purpose Flash 48 TFBGA 6x8x1.2 Mm T/R
• Manufacturer: Microchip Technology

Specifications of SST39VF1601C-70-4C-B3KE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39VF1601C/1602C also have the Auto Low
Power mode which puts the device in a near standby mode
after data has been accessed with a valid Read operation.
This reduces the I
to typically 3 µA. The Auto Low Power mode reduces the
typical I
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF1601C/1602C is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 6).
Word-Program Operation
The SST39VF1601C/1602C are programmed on a word-
by-word basis. Before programming, the sector where the
word exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 10
µs. See Figures 7 and 8 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 22 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
©2010 Silicon Storage Technology, Inc.
DD
active read current to the range of 2 mA/MHz of
DD
active read current from typically 9 mA
2
Any commands issued during the internal Program opera-
tion are ignored. During the command sequence, WP#
should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF1601C/1602C offer both Sec-
tor-Erase and Block-Erase mode.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on non-uniform
block sizes—thirty-one 32 KWord, one 16 KWord, two 4
KWord, and one 8 KWord blocks. See Figure 5 for top and
bottom boot device block addresses. The Sector-Erase
operation is initiated by executing a six-byte command
sequence with Sector-Erase command (50H) and sector
address (SA) in the last bus cycle. The Block-Erase opera-
tion is initiated by executing a six-byte command sequence
with Block-Erase command (30H) and block address (BA)
in the last bus cycle. The sector or block address is latched
on the falling edge of the sixth WE# pulse, while the com-
mand (30H or 50H) is latched on the rising edge of the
sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase operation can be
determined using either Data# Polling or Toggle Bit meth-
ods. See Figures 12 and 13 for timing waveforms and Fig-
ure 26 for the flowchart. Any commands issued during the
Sector- or Block-Erase operation are ignored. When WP#
is low, any attempt to Sector- (Block-) Erase the protected
block will be ignored. During the command sequence,
WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
2
toggling and DQ
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
6
at ‘1’. While in Erase-Suspend
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