XR16V794IV-0B-EVB Exar Corporation, XR16V794IV-0B-EVB Datasheet - Page 35

• Manufacturer Part Number: XR16V794IV-0B-EVB
• Description: Supports V794 64 Ld TQFP,ISA Interface
• Manufacturer: Exar Corporation

Specifications of XR16V794IV-0B-EVB

• Design Resources: XR17V798/794 Eval Board Schematic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
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MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
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This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic
1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity,
framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
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LSR[6]: Transmitter Empty Flag
This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR,
in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the
TX FIFO or TSR contains a data character.
LSR[5]: Transmit FIFO Empty Flag
This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new
character for transmission. This bit is set to a logic 1 when the last data byte is transferred from the transmit
FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the transmit
FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is cleared when
at a byte is written to the THR.
LSR[4]: Receive Break Flag
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LSR[3]: Receive Data Framing Error Flag
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LSR[2]: Receive Data Parity Error Flag
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4.8
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
Logic 0 = No FIFO error (default).
Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or logic 1.
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity
information and is suspect. This error is associated with the character available for reading in RHR.
Line Status Register (LSR) - Read Only
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
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XR16V794