XR16V794IV-0B-EVB Exar Corporation, XR16V794IV-0B-EVB Datasheet - Page 6
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XR16V794IV-0B-EVB
Manufacturer Part Number
XR16V794IV-0B-EVB
Description
Supports V794 64 Ld TQFP,ISA Interface
Manufacturer
Exar Corporation
Datasheet
1.XR16V794IV-F.pdf
(53 pages)
Specifications of XR16V794IV-0B-EVB
Design Resources
XR17V798/794 Eval Board Schematic
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
The XR16V794 (794) integrates the functions of 4 enhanced 16550 UARTs, a general purpose 16-bit timer/
counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt
source registers that provides interrupt-status for all 4 UARTs, timer/counter and a sleep wake up indicator.
Each UART channel has its own 16550 UART compatible configuration register set for individual channel
control, status, and data transfer. Additionally, each UART channel has 64-byte of transmit and receive FIFOs,
automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis control, automatic Xon/Xoff and special
character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters,
infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate generator with a prescaler of divide by
1 or 4, and data rate up to 8Mbps with 8X sampling clock or 4Mbps with 16X sampling clock. The XR16V794 is
a 2.25-3.6V device with 5 volt tolerant inputs (except XTAL1).
The RST# input resets the internal registers and the serial interface outputs in all 4 channels to their default
state (see
in the device.
The internal registers of each UART can be reset by writing to the RESET register in the Device Configuration
Registers. For more details, see the RESET register description on
A LOW on the chip select pin, CS#, allows the user to select one of the UART channels to configure, send
transmit data and/or unload receive data to/from the UART. When address line A7 = 0, address lines A6:A4
are used to select one of the eight channels. See
During a write cycle, the setting of the Device Configuration register REGB
override the channel selection of address A6:A4 and allow a simultaneous write to all 4 UART channels when
any channel is written to. This functional capability allow the registers in all 4 UART channels to be modified
concurrently, saving individual channel initialization time. Caution should be considered, however, when using
this capability. Any in-process serial data transfer may be disrupted by changing an active channel’s mode.
Also, REGB bit-0 should be reset to a logic 0 before attempting to read from the UART.
1.0 DESCRIPTION
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.1.1
2.1.2
Device Reset
UART Channel Selection
Simultaneous Write to All Channels
Table
Hardware Reset
Software Reset
19). A LOW pulse of longer than 40 ns duration will be required to activate the reset function
A7
0
0
0
0
A6
0
0
0
0
T
ABLE
A5
0
0
1
1
1: UART C
A4
Table 1
0
1
0
1
6
HANNEL
below for UART channel selection.
Channel 0 Selected
Channel 1 Selected
Channel 2 Selected
Channel 3 Selected
S
ELECTION
F
page
UNCTION
24.
(See Table
8) bit-0 to a logic 1 will
REV. 1.0.1